Credo Technology Group Limited

Oridus, Inc.

Xin Chang

Haoli Qian

Junqing Phil Sun

Kyungjin Kim

Fang Cai

Kuo-Chun Lee

Wenzhe Gao

Alex Nazari

Chad Cohen

Serializer/deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response ('FIR') filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

Serdes with robust parameter initialization

Integrated circuit transceivers having digital timing recovery loops with phase interpolation may incorporate dynamic loop gains to compensate for nonlinearities of the phase interpolation. An illustrative receiver circuit includes: a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator provides a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal. The timing error estimator produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.

Dynamic timing loop gain to compensate phase interpolation nonlinearities

A method and apparatus for inserting antenna diodes into an integrated circuit design is described. During the design process, diode cells are placed in filler cells of the integrated circuit design, but left unconnected. Subsequently, when an ECO is received requiring antenna diodes to be inserted in the integrated circuit design, only metal mask changes are required to connect the diode cells to gate electrodes of specified transistors or cells. Since the diode cells are already part of the original integrated circuit design layout, it is not necessary to perform a re-layout of the design cells with the diode cells performing antenna diode functions, thereby speeding up the EDA redesign process as well.

Method for inserting antenna diodes into an integrated circuit design

Growing community of inventors

Santa Clara, CA, United States of America

Xin Chang