Gowin Semiconductor Corporation

Lattice Semiconductor Corporation

Xiaozhi Lin

Jinghui Zhu

Jianhua Liu

Chienkuang Chen

Diwakar Chopperla

Ning Song

Tianping Wang

Zhenyu Gu

Tianxin Wang

Fei Song

Gyudong Kim

Min-Kyu Kim

Yu Shen

Gijung Ahn

Kexin Luo

Chwei-po Chew

Xiaofeng Wang

Qiming Wu

Guofu Peng

Qiang Zhou

Baoli Tong

Yunfeng Wang

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Method and system for organizing programmable semiconductor device into multiple clock regions

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer ('SerDes') region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions

A field-programmable gate array ('FPGA') contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals ('RCSs') generated from a clock source with a high clock signal quality (&#x201c;CSQ&#x201d;) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (&#x201c;NCSs&#x201d;) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (&#x201c;SCSs&#x201d;) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

Methods and apparatus for providing a clock fabric for an FPGA organized in multiple clock regions

A phase-locked loop (PLL) and a method for calibrating a VCO therein are provided. The PLL comprises a frequency-phase detector, a charge pump, a loop filter, a VCO, a divider and a calibration circuit. The calibration circuit is used to acquire a frequency of an output signal of the VCO, to calibrate the frequency of the output signal according to an expected frequency, and to acquire frequency control parameters of the VCO at the current signal frequency. The amplitude and gain of the output signal are kept constant according to the amplitude control parameters and gain control parameters. The PLL can meet the demands on frequencies of multiple protocols and can adaptively look up and stabilize the suitable frequency. It solves the issue that the amplitude of the output signal of the VCO is not constant when the PLL operates in a large frequency range.

Phase-locked loop and method for calibrating voltage-controlled oscillator therein

Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.

Successive approximation register-based analog-to-digital converter with increased time frame for digital-to-analog capacitor settling

Embodiments of the invention are generally directed to compensation for common mode signal swing. An embodiment of an apparatus includes a connector for the transfer of the data, the connector including connections for a first set of one or more conductors; a receiver for the reception of data via the connector, the received data including a first signal and a second signal transmitted via the set of one or more conductors, the second signal being a common mode signal modulating the first signal, the receiver including an amplifier to amplify the received data with a positive gain; and a common mode compensation circuit to compensate for a voltage swing of the common mode signal in the amplified received data. The common mode compensation circuit is to sense the common mode signal, amplify the sensed common mode signal with a negative gain, and feed back the amplified common mode to output nodes of the receiver.

Compensation scheme for MHL common mode clock swing

Embodiments of the invention are generally directed to charge pump calibration for a dual-path phase-locked loop circuit. An embodiment of an apparatus includes a phase frequency detector; an integral path including a first charge pump; a proportional path including a second charge pump; and a calibration mechanism for the first charge pump and the second charge pump, the calibration mechanism including a phase detector to detect whether a reference clock signal or a feedback clock signal is leading or lagging in phase and to generate a signal indicating which clock signal is leading or lagging, a first memory element and a second memory element to store the signal from the phase detector, a first control logic to adjust current for the first charge pump based on the value stored in the first memory element, and a second control logic to adjust current for the second charge pump based on the value stored in the second memory element.

Charge pump calibration for dual-path phase-locked loop

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Shanghai, China

Xiaozhi Lin