Sun Microsystems, Inc.

Oracle America, Inc.

Xiaozhen Guo

Ping Wang

Heechoul Park

Jungyong Lee

Tao-Ying Yau

A push-pull voltage regulator configured to selectively provide power to used portions of a memory array is presented. The push-pull voltage regulator includes a voltage-up regulator, which provides a reference voltage to an SRAM array, and a voltage-down regulator, which controls removal of excess charge from the SRAM array. The voltage-down regulator consists of a plurality of amplifier stages with a plurality of inputs, a plurality of inverters, a gain amplifier, a biasing transistor, and a NMOS drainage transistor. The gate terminal of the NMOS drainage transistor is coupled to an output of the voltage-down regulator. A first output terminal of the NMOS drainage transistor coupled to an output node of the push-pull voltage regulator and a second output terminal of the NMOS drainage transistor coupled to ground. When activated, the NMOS drainage transistor transfers excess charge from the SRAM array to ground.

Voltage regulator for write/read assist circuit

A system for minimizing the effect of clock skew in a precharge circuit includes a switch coupled between an input to the precharge circuit and a global bitline; and a control circuit coupled to a precharge component and the switch. The control circuit determines whether the switch and the precharge component are activated and the control circuit receives feedback from the switch. A method of minimizing the effect of clock skew in a precharge circuit includes controlling whether an input signal outputting a first signal and a second signal from the precharge circuit; controlling the outputting of the second signal from the precharge circuit based on a clock signal, a select signal, and a dynamic signal.

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Sunnyvale, CA, United States of America

Xiaozhen Guo