Beijing Baidu Netcom Science and Technology Co., Ltd.

Kunlunxin Technology (beijing) Company Limited

Baidu USA LLC

Baidu.com Times Technology (beijing) Co. Ltd.

Xiaozhang Gong

Jing Wang

Jian Ouyang

Hefei Zhu

Zhibiao Zhao

Qingshu Chen

Wei Qi

Yong Wang

Yupeng Li

Jiaxin Shi

Xianglun Leng

Hanlin Xie

Embodiments of the present disclosure propose a deep learning processing apparatus and method, device and storage medium, relating to the field of artificial intelligence. A deep learning processing apparatus includes: at least one matrix multiply-add module, configured to perform a matrix multiply-add operation of a convolution kernel parameter value matrix of a convolutional layer in a convolutional neural network and a first error gradient value matrix to obtain a plurality of intermediate matrices; a storage apparatus, configured to store the plurality of intermediate matrices without reshaping elements in the plurality of intermediate matrices; and a plurality of matrix accumulation modules, configured to read the plurality of intermediate matrices from the storage apparatus and perform a matrix accumulation operation based on the plurality of intermediate matrices according to a convolution scheme of the convolutional layer in parallel, to obtain a second error gradient value matrix for the convolutional layer.

Deep learning processing apparatus and method, device and storage medium

A method for data processing, a processor chip. The method includes: acquiring a first relationship instruction; executing at least one first computing instruction acquired before the first relationship instruction based on the first relationship instruction; and sending acknowledgment information based on the first relationship instruction in response to completing executing the at least one first computing instruction, to cause a second coprocessor receiving the acknowledgment information to revert to a state of acquiring a second computing instruction after the second relationship instruction acquired by a second coprocessor based on the acknowledgment information.

Synchronizing coprocessors using synchronization instructions to force a second coprocessor to wait until receiving an acknowledgement signal from a first coprocessor

A data processing system includes a central processing unit (CPU) and accelerator cards coupled to the CPU over a bus, each of the accelerator cards having a plurality of data processing (DP) accelerators to receive DP tasks from the CPU and to perform the received DP tasks. At least two of the accelerator cards are coupled to each other via an inter-card connection, and at least two of the DP accelerators are coupled to each other via an inter-chip connection. Each of the inter-card connection and the inter-chip connection is capable of being dynamically activated or deactivated, such that in response to a request received from the CPU, any one of the accelerator cards or any one of the DP accelerators within any one of the accelerator cards can be enabled or disabled to process any one of the DP tasks received from the CPU.

Distributed AI training topology based on flexible cable connection

Disclosed are an apparatus and method for transforming a matrix, and a data processing system. The apparatus may include: a first shift unit, configured to receive matrix data and perform first cyclic shift on the matrix data to generate first data; a cache unit, configured to write each row of data into the cache unit in the first data thereto in an order different from the order of respective data in the row of data to store the first data as second data; and a second shift unit, configured to read the second data from the cache unit and perform second cyclic shift on the second data to generate transformed matrix data.

Apparatus and method for transforming matrix, and data processing system

A method and apparatus for executing an instruction are provided. In the method, an instruction queue is first generated, and an instruction from the instruction queue in preset order is acquired. Then, a sending step including: determining a type of the acquired instruction; determining, in response to determining that the acquired instruction is an arithmetic instruction, an executing component for executing the arithmetic instruction from an executing component set; and sending the arithmetic instruction to the determined executing component is executed. Last, in response to determining that the acquired instruction is a blocking instruction, a next instruction is acquired after receiving a signal for instructing an instruction associated with the blocking instruction being completely executed.

Method and apparatus for executing instructions including a blocking instruction generated in response to determining that there is data dependence between instructions

Methods, apparatuses, devices, and storage media for performing a processing task are provided. A portion of portions of the processing task can include a group of operations that are to be performed at a processing unit of processing units. The group of operations can include operations of a first type and operations of a second type. In the method, a first queue for performing the operations of the first type and a second queue for performing the operations of the second type can be built, respectively. Based on a definition of the processing task, a dependency relationship between a group of operations to be performed at the processing unit and a group of operations to be performed at other processing units in the plurality of processing units can be obtained. Operations in the first queue and operations in the second queue can be performed respectively based on the dependency relationship.

Method, apparatus, device, and storage medium for performing processing task

Embodiments of the present disclosure relate to a method, an apparatus, an electronic device and a computer readable storage medium for determining connection relationships among a plurality of chips. The method includes determining identity information of a plurality of chips managed by a host, the plurality of chips being connected by respective inter-chip communication interfaces for inter-chip communication. The method further includes allowing one or more of the plurality of chips to acquire identity information of other chips connected to the inter-chip communication interface of the one or more chips. The method further includes reading identity information of the other chips by means of a management interface of the one or more chips with regard to communicating with the host, so as to determine connection relationships among the plurality of chips.

Method, apparatus, electronic device and computer readable storage medium for supporting communication among chips

The present disclosure relates to a method, an apparatus, an electronic device and a computer readable storage medium for accessing static random access memories. The method includes: receiving an access request for data associated with the static random access memories; writing a plurality of sections of the data into a plurality of different static random access memories in an interleaved manner in response to the access request being a write request for the data, each of the plurality of sections having its respective predetermined size; and reading the plurality of sections of the data from the plurality of static random access memories in an interleaved manner in response to the access request being a read request for the data, each of the plurality of sections having its respective predetermined size.

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Xiaozhang Gong