Marvell International Limited

Marvellworld Trade Ltd.

Nxp Usa, Inc.

Marvell Asia Pte., Ltd.

Xiaoyue Wang

Shafiq M Jamal

Weiwei Xu

Thomas B Cho

Prasanna Upadhyaya

Arvind Anumula Paramanandam

Hung Sheng Lin

Shingo Hatanaka

Ovidiu Carnu

Norman Liu

Xiang Yang Li

Ken Yeung

Ashutosh Verma

Alireza Razzaghi

Anuranjan Jha

Arvind Anumula Parmanandam

Chieh-Te Chang

One example discloses an analog to digital converter (ADC), including: an analog comparator configured to receive an analog input signal and in response generate a comparator output signal; a set of digital to analog converter (DAC) elements configured to receive the analog input signal; wherein the DAC elements are configured to generate an analog DAC output signal in response to a digital code and the analog input signal; wherein the comparator is configured to receive the analog DAC output signal; a feedback circuit configured to generate a first feedback signal and a second feedback signal from the comparator output signal; a controller configured to enable a first set of controller elements in response to the first feedback signal; wherein the controller configured to enable a second set of controller elements in response to the second feedback signal; and wherein the controller elements are configured to generate the digital code.

Multi-phase analog to digital converter (ADC)

Embodiments of a differential bootstrapped track-and-hold circuit are disclosed. In an embodiment, the differential bootstrapped track-and-hold circuit includes first and second single-ended bootstrapped track-and-hold circuits. Each single-ended bootstrapped track-and-hold circuit includes a sampling switch connected between an input terminal and an output terminal, a sampling capacitor connected to the output terminal, and a dummy sampling switch connected between the input terminal and a dummy output terminal. The sampling switch and the dummy sampling switch are controlled by a bootstrap driver connected to the input terminal. The dummy output terminal of the first single-ended bootstrapped track-and-hold circuit is connected to the output terminal of the second single-ended bootstrapped track-and-hold circuit and the dummy output terminal of the second single-ended bootstrapped track-and-hold circuit is connected to the output terminal of the first single-ended bootstrapped track-and-hold circuit to provide signals to compensate for charge injection errors at the output terminals.

Differential bootstrapped track-and-hold circuit with cross-coupled dummy sampling switches

A reconfigurable regulator includes an error amplifier configured to generate a difference signal indicative of a voltage difference between a reference analog signal and a feedback analog signal; a pulse width modulation generator configured to receive the difference signal, and to generate a first pulse width modulated signal in a linear mode and a second pulse width modulated signal in a switching mode; and a digital multiplexer (MUX) configured to receive a mode selection signal, the first pulse width modulated signal and the second pulse width modulated signal. The digital MUX outputs one of the first pulse width modulated signal or the second pulse width modulated signal based on the mode selection signal. The reconfigurable regulator further includes a digital driver configured to receive one of the first pulse width modulated signal or the second pulse width modulated signal and to output a digital control signal based on the received one of the first pulse width modulated signal or the second pulse width modulated signal.

Reconfigurable regulator for regulating power in linear and switching modes

Embodiments described herein provide a voltage regulator that includes an error amplifier configured to provide a difference signal indicative of a voltage difference between a reference signal and a feedback signal, a pulse width modulation generator configured to receive the difference signal and to output a pulse width modulated signal based on the difference signal, and one or more transistors configured to receive the pulse width modulated signal at a gate of the one or more transistors, and to provide the feedback signal at a drain of the one or more transistors as a regulated voltage that is adjusted to match the reference signal so as to reduce the voltage difference between the reference signal and the feedback signal.

Class-D driven low-drop-output (LDO) regulator

A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.

Switched-capacitor bandgap reference circuit using chopping technique

An Analog-to-Digital Converter (ADC) device includes an input interface and conversion circuitry. The input interface is configured to receive an analog input signal. The conversion circuitry is configured to convert the analog input signal into a digital word by performing a sequence of iterations to determine respective bits of the digital word, wherein the sequence (i) progresses in descending order of bit significance of the bits, from a Most Significant Bit (MSB) to a Least Significant Bit (LSB), and (ii) repeats evaluation of a predefined number of Least-Significant Bits (LSBs) of the digital word multiple times, and determining a final value of the digital word by averaging the repeatedly-evaluated LSBs.

Power-efficient successive-approximation analog-to-digital converter using LSB averaging

Systems and techniques relating to a digital-to-analog converter (DAC) are described. A described DAC cell includes a differential switch pair coupled with a cross-coupled switch pair. Gate terminals of the differential switch pair are arranged to respectively receive an input signal to the cell and an inverted version of the input signal to respectively drive the gate terminals of the differential switch pair. Gate terminals of the cross-coupled switch pair are arranged to respectively receive the input signal and the inverted version of the input signal to respectively drive the gate terminals of the cross-coupled switch pair. The cross-coupled switch pair is configured to reduce or eliminate net differential transient current between switch output terminals of the differential switch pair. A current-to-voltage converter coupled with the switch output terminals of the differential switch pair generates a voltage that forms at least a portion of an output of the digital-to-analog converter.

Current steering cell with code-dependent nonlinearity cancellation and fast settling for low-power low-area high-speed digital-to-analog converters

A system including first and second plurality of conductors stacked along a first axis on a substrate. The first axis is perpendicular to a plane on which the substrate lies. In the first and second plurality of conductors, each conductor is connected to an adjacent conductor by one or more first vias arranged along the first axis. The first and second plurality of conductors are arranged in parallel along a second axis (i) perpendicular to the first axis and (ii) parallel to the plane on which the substrate lies. The first plurality of conductors respectively lie on a plurality of planes (i) perpendicular to the first axis and (ii) parallel to the plane on which the substrate lies. The second plurality of conductors respectively lie on the plurality of planes. Capacitances are formed along the plurality of planes between the first plurality of conductors and the second plurality of conductors.

Stackable high-density metal-oxide-metal capacitor with minimum top plate parasitic capacitance

Circuits having corresponding methods and computer-readable media comprise: an amplifier; a crystal port configured to be electrically coupled to a crystal, wherein a first terminal of the crystal port is electrically coupled to an input of the amplifier, and wherein a second terminal of the crystal port is electrically coupled to an output of the amplifier; a first capacitor, wherein a first terminal of the first capacitor is electrically coupled to ground; a second capacitor, wherein a first terminal of the second capacitor is electrically coupled to ground; a first switch configured to selectively electrically couple the input of the amplifier to a second terminal of the first capacitor; and a second switch configured to selectively electrically couple the output of the amplifier to a second terminal of the second capacitor.

Crystal oscillator with low-power mode

In aspects of a low phase noise technique for use with a crystal oscillator, a bias control circuit sets a bias voltage on the gate of a first transistor needed to sink or source an amount of current corresponding to a sensed common mode signal. The sensed common mode signal is sensed with a common mode sense circuit that is coupled across two ports of the crystal oscillator, and current is provided by a current source. The bias voltage is set by a bias controller that uses a second transistor coupled to the common mode sense circuit and the first transistor.

Low phase noise technique for a crystal oscillator circuit

The present disclosure describes apparatuses and techniques for detection of an external oscillator. In some aspects, an integrated circuit includes an oscillator detector coupled to an external electrical connection. The oscillator detector may include a transistor having a gate coupled to the external electrical connection that is configured to detect a presence of an external oscillator.

External oscillator detector

The present disclosure describes apparatuses and techniques for low-noise regulation of battery power. In some aspects an indication of a voltage level of a battery supplying power to a linear regulator is received, an output voltage level is determined for the linear regulator that permits the linear regulator to operate in an active condition in which noise of the power supplied by the battery is mitigated, and the linear regulator is configured to output the regulated power at the output voltage level effective to provide low-noise regulated power for components of a device.

Low-noise regulation of battery power

A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Growing community of inventors

Santa Clara, CA, United States of America

Xiaoyue Wang