Sandisk Technologies Inc.

Xiaoyu Che

Yanjie Wang

Guirong Liang

Yi Song

Shota Murai

Runchen Fang

A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: determine, based on a stage of a product lifetime of the non-volatile memory, a negative word line setting for implementing during performance of a first operation; perform the first operation, the first operation including adjusting, based on the negative word line setting, a negative word line relative parameter; determine, based on another stage of the product lifetime of the non-volatile memory, another negative word line setting for implementing during performance of a second operation; and perform the second operation, the second operation including adjusting, based on the other negative word line setting, another negative word line relative parameter.

Adaptive negative word line voltage

A memory device includes a plurality of memory cells and control circuitry configured to perform a foggy-fine programming operation in which memory cells are programmed in multiple programming passes. To perform the foggy-fine programming operation, the control circuity is configured to perform a first pass of the foggy-fine programming operation on the memory cells, perform, in accordance with a first sense time, a first sensing operation on the memory cells programmed in the first pass of the foggy-fine programming operation, perform a second pass of the foggy-fine programming operation on the memory cells previously programmed in the first pass of the foggy-fine programming operation, and perform, in accordance with a second sense time, a second sensing operation on the memory cells programmed in the first pass and the second pass of the foggy-fine programming operation, wherein the second sense time is different from the first sense time.

Sense time separation in foggy-fine program to improve optimal VT width

The memory device includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is provided, and the controller is configured to program the memory cells to respective threshold voltages in a programming operation. The controller is configured to, in the programming operation, apply a first voltage to a control gate of a selected word line of the plurality of word lines. The controller is also configured to continuously ramp a voltage applied to the control gate of the selected word line from the first voltage to a programming voltage over a first duration. The controller is further configured to hold the voltage applied to the control gate of the selected word line at the programming voltage over a second duration that is less than the first duration.

Programming techniques to reduce programming stress in a memory device

A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation. The control means is also configured to program the drain-side select gate transistors of the memory holes to a target transistor threshold voltage using pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation. The first transistor step amount is greater than the second transistor step amount.

Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates

A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to offset at least one of a bit line settling time and a kick voltage during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.

Utilizing data pattern effect to control read clock timing and bit line kick for read time reduction

The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells of the plurality of word lines to a plurality of data states in a multi-pass programming operation. A later programming pass of the multi-pass programming operation includes a plurality of programming loops with incrementally increasing programming pulses. For at least one data state, the later programming pass includes maintaining a count of the programming loops of the later programming pass. The later programming pass also includes inhibiting or slowing programming of the memory cells being programmed to one of the data states during a predetermined program count verify (PCV) programming loop and a PCV&#x2212;1 programming loop and skipping a verify operation for all programming loops prior to a PCV+1 programming loop.

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San Jose, CA, United States of America

Xiaoyu Che