Intel Corporation

Xiaoye Qin

Nicholas G Minutillo

Johann Christian Rode

Suresh Vishwanath

Robert Ehlert

Patrick M Wallace

Michael S Beumer

Atsunori Tanaka

Gregory P McNerney

Sanyam Bajaj

In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.

Gate structures to enable lower subthreshold slope in gallium nitride-based transistors

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Beaverton, OR, United States of America

Xiaoye Qin