Peking University

State Grid Corporation of China

Clp Puri Zhangbei Wind Power Research & Testing Co

China Electric Power Research Institute Company Li

Xiaoyan Xu

Ru Huang

Jiewen Fan

Jia Qi Li

Runsheng Wang

Li Wang

Shuai Sun

Nan Zhang

Chun Yen Liu

Xiaofei Li

Yujie Ai

Zhihua Hao

Shuangshuang Pu

Yujie Al

Chi Yang Li

Yanping Xu

Yuehui Huang

Weisheng Wang

Yuefeng Wang

Cun Dong

Yunfeng Gao

Xiaofeng Pan

A method and device for modeling a long-time-scale photovoltaic output time sequence are provided. The method includes that: historical data of a photovoltaic power station is acquired, and a photovoltaic output with a time length of one year and a time resolution of 15 mins is selected (); weather types of days corresponding to the photovoltaic output are acquired from a weather station (), and probabilities of transfer between each type of weather are calculated respectively (); and a simulated time sequence of the photovoltaic output within a preset time scale is generated (), and its validity is verified (). By the method, annual and monthly photovoltaic output simulated time sequences consistent with a random fluctuation rule of a photovoltaic time sequence may be acquired according to different requirements to provide a favorable condition and a data support for analog simulation of time sequence production including massive new energy.

Method and device for modeling a long-time-scale photovoltaic output time sequence

Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed. Further, the power consumption of the device can be further reduced through the special multi-threshold characteristic of the device with separated double gates.

Method for fabricating FinFET with separated double gates on bulk silicon

The present invention discloses a method of adjusting a threshold voltage of a multi-gate structure device, wherein, preparing the multi-gate structure device to be formed to have a channel impurity distribution with high doping on surface and lowly doping inside, where while a threshold voltage is adjusted by using impurity doping, the influences of the Coulomb impurity scattering on the carriers is reduced as much as possible, so that the mobility of the carriers is maintained at a higher level. Firstly, the present solution is able to make a multi-gate device obtain a larger range of a multi-threshold voltage; it is convenient for the various demands of the device in the circuit designing by IC designers. Secondly, in the course of introducing the impurity doping to adjust a threshold voltage, the influences of the Coulomb impurity scattering on the channel carrier are reduced as much as possible, so that the mobility of the charge carriers is maintained at a higher level, and the device is ensured to have a higher drive current. Finally, the present solution is achieved by the process method compatible with a conventional CMOS, and has the potential for a large scale production.

Method of adjusting a threshold voltage of a multi-gate structure device

A method for fabricating a multi-gate structure device with a source and a drain having a quasi-SOI structure, comprising forming an active region in a shape of a fin bar, forming an oxide isolation layer for shallow trench isolation (STI), forming a polysilicon dummy gate, forming source and drain extension regions, forming the source and the drain with the quasi-SOI structure, and forming a high-K metal gate. Solution(s) consistent with the present innovations may be achieved by using a process method compatible with the conventional bulk silicon CMOS processes and can be easily integrated into the process flow. Moreover, innovations here may provide a small leakage current even in a case of having a short channel length, thereby reducing the power consumption of the device.

Method for fabricating multi-gate structure device with source and drain having quasi-SOI structure

Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Field effect transistor with a vertical channel and fabrication method thereof

Disclosed herein is a method for fabricating an ultra fine nanowire, which relates to a manufacturing technology of a microelectronic semiconductor transistor. This method obtains a suspended ultra fine nanowire base on a combination of a mask blocking oxidation process and a stepwise oxidation process. A diameter of the suspended ultra fine nanowire fabricated by this method is precisely controlled to 20 nm by controlling a thickness of a deposited silicon nitride film and a time and temperature of the two oxidation process. Since a speed of a dry oxidation process is slower, the size of the final nanowire may be precisely controlled. This method can be used to fabricate an ultra fine nanowire with a lower cost and a higher applicability.

Method for fabricating ultra-fine nanowire

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Beijing, China

Xiaoyan Xu