Yangtze Memory Technologies Co., Ltd.

Xiaoxin Liu

Lei Xue

Tingting Gao

Wanbo Geng

Bo Huang

Jiaqian Xue

Zhiliang Xia

Weihua Cheng

Chia-Chann Shiue

Lan Yao

Xiaolong Du

Changzhi Sun

A method for forming a three-dimensional memory device includes forming an alternating dielectric stack on a substrate and forming an opening extending partially through the alternating dielectric stack. The opening exposes sidewalls of the alternating dielectric stack. The method also includes disposing a protection layer in the opening and on the exposed sidewalls of the alternating dielectric stack. The method further includes extending the opening through the alternating dielectric stack and forming channel layers in the extended opening.

Channel structures for three-dimensional memory devices and methods for forming the same

A three-dimensional (3D) memory device includes a first stack structure, a first channel structure, a second stack structure, and a second channel structure. The first stack structure includes interleaved first conductive layers and first dielectric layers. The first channel structure extends through the first stack structure along a first direction. The first channel structure includes a first semiconductor channel, and a first memory film over the first semiconductor channel. The first memory film includes a storage layer. The storage layer is separated by the first dielectric layers into a plurality of sections.

Three-dimensional memory device with restrained charge migration and method for forming the same

Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion.

Three-dimensional memory devices with reduced cell interference and fabrication methods thereof

A three-dimensional (3D) memory device includes a stack structure and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers. The channel structure extends through the stack structure along a first direction. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. The blocking layer and the storage layer are separated by the dielectric layers into a plurality of sections.

Three-dimensional memory device with improved charge lateral migration and method for forming the same

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes a plurality of semiconductor channels in the plurality of petals, respectively.

Three-dimensional memory devices with channel structures having plum blossom shape

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a charge trapping layer, a tunneling layer, a semiconductor channel, and a channel plug. The channel plug is above and in contact with the charge trapping layer, the tunneling layer, and the semiconductor channel.

Three-dimensional memory devices with channel structures having plum blossom shape and methods for forming the same

The present disclosure provides a method of processing a semiconductor device having a stack formed over a source sacrificial layer above a substrate, a channel structure extending vertically through the stack and the source sacrificial layer, a gate line cut trench extending vertically through the stack, and a spacer layer covering uncovered top and side surfaces of the stack. The method can include exposing a lower sidewall of the channel structure by removing the source sacrificial layer, forming a protection layer on all uncovered surfaces, exposing a channel layer of the channel structure by removing a first portion of the protection layer and an insulating layer of the channel structure, forming an initial source connection layer over the exposed channel layer, exposing the substrate by removing a second portion of the protection layer, and forming a source connection layer over the initial source connection layer and the exposed substrate.

Two-step L-shaped selective epitaxial growth

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed on the substrate and including a plurality of interleaved conductive layers and dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and having a plurality of protruding portions abutting the conductive layers and a plurality of normal portions abutting the dielectric layers. Each of the plurality of channel structures includes a blocking layer along a sidewall of the channel structure, and a storage layer over the blocking layer. The storage layer includes a plurality of charge trapping structures in the protruding portions of the channel structure, and a plurality of protecting structures in the normal portions of the channel structure and connecting the plurality of charge trapping structures.

Channel structures having protruding portions in three-dimensional memory device and method for forming the same

A three-dimensional (3D) memory device includes a memory stack including conductive layers and dielectric layers interleaving the conductive layers, and a channel structure extending through the memory stack along a vertical direction. The channel structure has a plurality of protruding portions protruding along a lateral direction and facing the conductive layers, respectively, and a plurality of normal portions facing the dielectric layers, respectively, without protruding along the lateral direction. The channel structure includes a plurality of blocking structures in the protruding portions, respectively, and a plurality of storage structures in the protruding portions and over the plurality of blocking structures, respectively. A vertical dimension of each of the blocking structures is nominally the same as a vertical dimension of a respective one of the storage structures over the blocking structure.

A first opening extending vertically through a dielectric stack is formed above a substrate. The dielectric stack includes vertically interleaved dielectric layers and sacrificial layers. Parts of the sacrificial layers facing the opening are removed to form a plurality of first recesses. A plurality of stop structures are formed along sidewalls of the plurality of first recesses. A plurality of storage structures are formed over the plurality of stop structures in the plurality of first recesses. The plurality of sacrificial layers are removed to expose the plurality of stop structures from a plurality of second recesses opposing the plurality of first recesses. The plurality of stop structures are removed to expose the plurality of storage structures. A plurality of blocking structures are formed over the plurality of storage structures in the plurality of second recesses.

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following the plum blossom shape are formed from outside to inside in this order along sidewalls of the channel hole. A plurality of separate semiconductor channels each disposed over part of the continuous tunneling layer at a respective apex of the plum blossom shape are formed.

Methods for forming three-dimensional memory devices with channel structures having plum blossom shape

A method for forming a 3D memory device is provided. The method comprises forming a sacrificial layer on a substrate, forming an alternating dielectric stack on the sacrificial layer, forming a plurality of channel holes vertically penetrating the alternating dielectric stack and the sacrificial layer, and forming a first channel layer in each channel hole. The method further comprises forming a second channel layer on the first channel layer in each channel hole, such that a merging point of the second channel layer is higher than a bottom surface of the alternating dielectric stack. The method further comprises removing the sacrificial layer to form a horizontal trench, and forming a selective epitaxial growth layer in the horizontal trench.

Three-dimensional memory devices and fabricating methods thereof

A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.

Three-dimensional NAND memory device with split gates

A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.

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Wuhan, China

Xiaoxin Liu