Shenzhen China Star Optoelectronics Technology Co., Ltd.

Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Tcl China Star Optoelectronics Technology Co., Ltd.

Other

Xiaowen Lv

Chihyu Su

Chihyuan Tseng

Hejing Zhang

Wenhui Li

Longqiang Shi

Shimin Ge

Shujhih Chen

Chih-Yu Su

Yutong Hu

Zhiyuan Zeng

Yifang Chou

Yifan Wang

Congwei Liao

Chih Hao Wu

Haiyan Quan

Yanhong Meng

Wenlin Mei

Pojen Chiang

Chih-yuan Tseng

Renlu Chen

The disclosure provides an array substrate and a display panel. The array substrate includes a plurality of data lines, a plurality of scan lines, a plurality of clock signal lines, and a plurality of pixel units formed by the data lines and the scan lines horizontally and vertically crossing each other. The data lines are disposed between two adjacent columns of the pixel units. The scan lines are disposed between two adjacent rows of the pixel units. The clock signal lines in an opening area of the pixel units are disposed in a plurality of orthographic projection areas of a plurality of trunk electrodes, are parallel to the data lines, and are disposed in a different layer from a pixel electrode.

Array substrate and display panel

A GOA circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. Each GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor. An AC signal applied to the pull-up module has high and low voltage levels. The high voltage level of the AC signal could reduce the rising time and the falling time of the conventional clock signal such that the output of the scan signal could be better. The low voltage level of the AC signal could pull down the signal in the blank time to perform a stress recovery such that the threshold voltage shift of the transistor caused by the high voltage level stress is reduced. This could raise the stability and the lifetime of the circuit.

Goa circuit and display panel for reducing threshold voltage shift of transistor by pulling down signal during blank time of scan signal

A GOA circuit and a display panel are disclosed. The GOA unit includes a plurality of stages of cascaded GOA units. Each GOA unit includes a pull-up control module, a pull-up module, a down transmission module, a pull-down remaining module, a pull-down module and a bootstrap capacitor. The pull-up module is deployed with two thin-film transistors, to which different oscillating signals are inputted, having individual output ports. The two transistors can operate alternatively for reducing the time a single thin-film transistor operates, lowering the shift of a threshold voltage and extending a lifespan of the device.

GOA circuit and display panel

The present invention provides a driving circuit and a display panel including at least two gate driving units, and at least two of the gate driving units are connected in a cascade arrangement. an Nth stage driving unit in the at least two of the gate driving units includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a bootstrap capacitor, wherein N is an integer greater than 0.

Driving circuit and display panel

The present application discloses an array substrate and a liquid crystal display panel. The array substrate includes an underlay substrate, a first electrode layer, a protection layer, and a second electrode layer that are disposed sequentially. The second electrode layer includes a pixel electrode, and the pixel electrode includes a pixel electrode main body and a conductive portion connected to each other. A rough surface is disposed on the conductive portion for draining redundant alignment liquid on the conductive portion such that a thickness of an alignment layer formed by curing the alignment liquid is even.

Array substrate and liquid crystal display panel

An array substrate and a display panel are provided. The array substrate includes a base substrate and a plurality of pixel units distributed in an array on the base substrate. The pixel unit includes a common electrode and a pixel electrode positioned above the common electrode. Meanwhile, the pixel electrode includes a main electrode and a branch electrode electrically connected to the main electrode, and an orthographic projection of the common electrode on the base substrate coincides with at least a part of an orthographic projection of the main electrode on the base substrate.

A gate-on-array (GOA) driving circuit is provided, and the GOA driving circuit includes a plurality of cascading GOA driving units. Each of the GOA driving units further includes a first GOA driving sub-unit including a first signal source and a second GOA driving sub-unit including a second signal source. The first GOA driving sub-unit operates when the first signal source transmits a first signal with a high voltage, and the second GOA driving sub-unit transmitting a second signal operates when the first signal source transmits the first signal with a low voltage.

Gate-on-array driving circuit

The present invention provides an array substrate and a liquid crystal display panel. The array substrate includes a substrate, a scan line, a data line, a thin film transistor, and a pixel electrode. The pixel electrode includes a trunk region and a branch region. In the pixel electrode, the data line is disposed along the trunk region. The present invention, by disposing the opaque data line in a region in which a trunk region of the opaque pixel electrode is located, reduces opaque regions of the array substrate and enhance the aperture ratio of the array substrate, which facilitates display quality of the liquid crystal display panel.

A thin film transistor array substrate includes: a substrate on which a thin film transistor and a storage capacitor are formed. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.

Thin-film transistor array substrate and manufacturing method thereof

A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.

Structure of oxide thin film transistor

The invention discloses an alignment method of a liquid crystal display panel including the following steps: assembling a color filter substrate, an array substrate and a liquid crystal layer into a liquid crystal display panel; applying a first alignment voltage to a common electrode line layer of the array substrate, applying a second alignment voltage to a common electrode layer of the color filter substrate, and a predetermined voltage difference existed between the first alignment voltage and the second alignment voltage; performing alignment to the liquid crystal layer of the liquid crystal display panel by the predetermined voltage difference, to make liquid crystal molecules in the liquid crystal layer arranged with a preset tilt angle; and irradiating the liquid crystal layer with an ultraviolet ray. The effect of alignment can be improved, the dependence of liquid crystal alignment on the data line can be reduced, and improves the product yield.

Alignment method of liquid crystal display panel

A GOA drive circuit includes a multiple stage of GOA drive units. A GOA drive unit includes a pre-pulldown unit which is configured to disconnect a discharge path of a first voltage signal via the pull-down sustaining unit before the first voltage signal jumps from a low electric potential to a high electric potential. In the GOA drive circuit, the voltage stability of the key nodes in a circuit and the reliability of the timing can be ensured; overall performance of the GOA drive circuit can be improved; and a service life of a display device can be prolonged.

GOA drive circuit

The invention provides a GOA circuit, other than the first to the fourth GOA units, in each GOA unit: the first pull-down maintenance module receives the first control signal, low voltage signal, scan signal and circuit start signal, and is connected to the first node, wherein the 52TFT of the first pull-down maintenance module has a gate connected to the first node, a source receives the circuit start signal, and a drain connected to the gates of the 31TFT and 41TFT so that when the first node is at high voltage, the gate-source voltage difference of the 31TFT and the 41TFT are both negative to effectively reduce the current leakage and prevent the current leakage from affecting the voltage of the first node, to improve the circuit stability without additional signal lines, able to facilitate production cost reduction and achieving narrow border design.

Gate driver on array having a circuit start signal applied to a pull-down maintenance module

A method of improving a high current of GOA circuit when power on is provided, including: determining a GOA circuit, wherein the GOA circuit includes a plurality of GOA structure units in cascade, each of GOA structure units includes a pull-up control circuit, a pull-up circuit, a transfer circuit, a pull-down circuit, a pull-down holding circuit and a bootstrapping capacitor, and a pre-charge signal, a first clock signal and a second clock signal are disposed on each of GOA structure units; and pulling up a voltage of the first clock signal and the second clock signal to a predetermined value for a certain time at an abnormal power off moment to discharge the pre-charge signal when detecting the GOA circuit abnormally power off. By practice of the disclosure, the pre-charge signal of GOA structure unit could discharge when the GOA circuit abnormally power off to reduce the high current probability.

Method of improving a high current of GOA circuit when power on

Disclosed is a manufacturing method of an array substrate, comprising steps of: depositing a first metal layer on a substrate; depositing a gate insulating layer on the substrate and the first metal layer, and forming a first via hole in the in-plane region of the gate insulating layer; depositing a second metal layer in an in-plane region and an out-of-plane of the gate insulating layer, wherein the second metal layer located in the in-plane region fills the first via hole; depositing a passivation layer on the second metal layer and the gate insulating layer, and forming a second via hole in the in-plane region of the passivation layer; forming a third via hole and a fourth via hole in the out-of plane region of the passivation layer, respectively; depositing a transparent conductive layer in the in-plane region and in the out-of-plane region of the passivation layer, respectively.

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Guangdong, China

Xiaowen Lv