Alibaba Group Holding Limited

T-Head (Shanghai) Semiconductor Co., Ltd.

Xiaowei Jiang

Jian Feng Chen

Shu Li

Jian Chen

Liang Han

Xiaoyu Zhang

An apparatus for operating an input/output (I/O) interface in a virtual machine is provided. The apparatus is configured to: map a first portion of a memory device to a configuration space of an I/O interface; obtain a first mapping table that maps a set of host space virtual addresses to a first set of physical addresses associated with the first portion of the memory device; obtain a second mapping table that maps a second set of physical addresses associated with a second portion of the memory device accessible by a virtual machine to the set of host space virtual addresses; generate a third mapping table that maps the second set of physical addresses to the first set of physical addresses; and provide the third mapping table to a device driver operating in the virtual machine, to enable the device driver to access the configuration space of the I/O interface.

Method and apparatus for hardware virtualization

The present disclosure relates to a unified memory apparatus having a unified storage medium and one or more processing units. The unified memory apparatus can include a first storage module having a first plurality of storage cells, and a second storage module having a second plurality of storage cells, each of the first and second plurality of storage cells configured to store data and to be identified by a unique cell identifier. The one or more processing units are in communication with the unified storage medium and the processing units are configured to receive a first input data from one of the first plurality of storage cells, receive a second input data from one of the second plurality of storage cells, and generate an output data based on the first and second input data.

Unified memory organization for neural network processors

The processing load on a host processor is substantially reduced by offloading the transport layer security protocol, such as the TLS/SSL protocol, the transport layer protocol stack, such as the TCP/IP protocol stack, and the network control required to access a network, such as the Internet, onto an expansion device.

Method, device, and system for offloading algorithms

A System-on-Chip (SoC) performs secure communication operations. The SoC may include a peripheral interface configured to communicate with a host system. The SoC may also include a network interface configured to receive network packets in a secure communication session. The SoC may further include a processor configured to execute an Operating System (OS) software and a secure communication software stack to process at least one received network packet in the secure communication session. In addition, the SoC may include a secure communication engine configured to perform cryptographic operations and generate at least one decrypted packet in the secure communication session. The at least one decrypted packet may be provided to the host system via the peripheral interface.

Secure communication acceleration using a System-on-Chip (SoC) architecture

The present application provides methods and systems for memory management of a kernel space and a user space. An exemplary system for memory management of the kernel space and the user space may include a first storing unit configured to store a first root page table index corresponding to the kernel space. The system may also include a second storing unit configured to store a second root page table index corresponding to the user space. The system may further include a control unit communicatively coupled to the first and second registers and configured to: translate a first virtual address to a first physical address in accordance with the first root page table index for an operating system kernel, and translate a second virtual address to a second physical address in accordance with the second root page table index for a user process.

Methods and systems for memory management of kernel and user spaces

A computer system is presented. The computer system comprises a memory system that stores data, a computer processor, and a memory access engine. The memory access engine is configured to: receive a first instruction of a computing process from the computer processor, wherein the first instruction is for accessing the data from the memory system; acquire at least a part of the data from the memory system based on the first instruction; and after the acquisition of the at least a first part of the data, transmit an indication to the computer processor to enable the computer processor to execute a second instruction of the computing process.

Method and apparatus for providing accelerated access to a memory system

The present disclosure provides systems and methods for executing instructions. The system can include: processing unit having a core configured to execute instructions; and a host unit configured to: compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein the set of instructions each includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions, and provide the set of instructions to the core.

System and method for executing instructions

An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.

Programmable multiply-add array hardware

The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.

Centralized-distributed mixed organization of shared memory for neural network processing

The present disclosure relates to a computing device with a multiple pipeline architecture. The multiple pipeline architecture comprises a first and second pipeline for which are concurrently running, where the first pipeline runs at least one cycle ahead of the second pipeline. Special number detection is utilized on the first pipeline, where a special number is a numerical value which yields a predictable result. Upon the detection of a special number, a computation is optimized.

Multiple-pipeline architecture with special number detection

The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.

Memory apparatus and method for controlling the same

A cache is presented. The cache comprises a tag array configured to store one or more tag addresses, a data array configured to store data acquired from a dynamic random access memory device, and a cache controller. The cache controller is configured to: receive a cache access request; determine, based on an indication associated with the cache access request, a cache access policy; and perform an operation to the tag array and to the data array based on the determined cache access policy.

Cache devices with configurable access policies and control methods thereof

An apparatus for operating a storage system is provided. The apparatus is coupled with one or more storage devices and one or more controllers and comprises a data request input module configured to receive a request for data and determine a data stripe that includes the requested data. The apparatus further comprises a controller instruction module configured to instruct one or more controllers to perform a decoding of code words of the determined data stripe, wherein the code words are acquired by the controllers from the one or more storage devices, and determine, based on error status information associated with the decoding, an error handling operation on the data stripe to modify one or more code words of the data stripe. The apparatus also comprises a data packaging module configured to generate the requested data based on the modified at least one or more code words.

Growing community of inventors

San Mateo, CA, United States of America

Xiaowei Jiang