Micron Technology Incorporated

Xiaosong Zhang

Yi Hu

David A Kewley

Chandra S Tiwari

Wei Yeeng Ng

Stephen J Kramer

Matthew J King

Jonathan D Harms

Daniel Billingsley

Richard T Housley

Tom Jibu John

Nikolay A Mirin

Robert Dembi

Adam L Olson

Biow Hiem Ong

Tien Minh Quan Tran

Yongjun Jeff Hu

Lifang Xu

Robert J Hanson

Suresh Ramarajan

Yiping Wang

Andrew Li

Merri Lyn Carlson

Ramey M Abdelrahaman

Lance Williamson

Keen Wah Chow

Narula Bilik

Michael J Irwin

Chao Zhu

Md Zakir Ullah

Kok Siak Tang

Md Zahid Hossain

Mohammad Moydul Islam

Zhigang Yang

Hui Chin Chong

Zhenyu Bo

Joan M Kash

David Neumeyer

Yung K Pak

John David Hopkins

Justin B Dorhout

Jian Li

Harsh Narendrakumar Jain

Matthew Park

Rohit Kothari

Shruthi Kumara Vadivel

Matthew Holland

Jason Reece

Michael E Koltonski

Bo Zhao

Michael J Gossman

Martin Jared Barclay

Joel D Peterson

Chandra Tiwari

Deep Panjwani

Kah Sing Chooi

Zhen Feng Yow

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.

Microelectronic devices including slot structures, and related electronic systems and methods of forming the microelectronic devices

A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

Microelectronic devices including stadium structures

A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

Wafer registration and overlay measurement systems and related methods

Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

Microelectronic devices with tiered decks of aligned pillars exhibiting bending and related methods

In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

Memory arrays and methods used in forming a memory array comprising strings of memory cells

An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

Apparatus and memory device including conductive lines and contacts, and methods of forming an apparatus including conductive lines and contacts

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

Electronic devices comprising overlay marks, memory devices comprising overlay marks, and related methods

Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, 'pillar density' being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Microelectronic devices with tiered decks of differing pillar density and related methods and systems

A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

Wafer alignment markers, systems, and related methods

Apparatus comprising structures including contact vias and conductive lines, related methods, and memory devices

Growing community of inventors

Boise, ID, United States of America

Xiaosong Zhang