Csmc Technologies Fab1 Co., Ltd.

Csmc Technologies Fab2 Co., Ltd.

Cmsc Technologies Fab1 Co., Ltd.

Xiaoshe Deng

Genyi Wang

Qiang Rui

Dongfei Zhou

Shuo Zhang

Shengrong Zhong

Wanli Wang

Xuan Huang

Shengrong Zong

A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure () and an active region (). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (). A plurality of notches () which penetrate through the back-surface P-type structure () from the back-surface metal layer () to the electric field stop layer () are formed in the active region (), and metals of the back-surface metal layer () are filled into the notches () to form a metal structure which extends into the electric field stop layer ().

Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor

An insulated gate bipolar transistor () is provided. A substrate () of the insulated gate bipolar transistor () is of an N type. A P-type region () is disposed on a back of the N-type substrate. A back metal structure () is disposed on a back of the P-type region (). A terminal protection ring is disposed in a terminal structure. A polysilicon gate () is disposed on a front surface of the substrate () in an active region. Sidewalls () are disposed at two sides of the polysilicon gate () on the substrate (). An interlayer medium () covered with the polysilicon gate () and the sidewalls () is disposed on the substrate (). The interlayer medium () is covered with a metal lead wire layer (). An N-type carrier enhancement region () is disposed in the substrate () in the active region. A P-type body region () is disposed in the carrier enhancement region (). An N-type heavily doped region () is disposed in the P-type body region (). A P-type heavily doped region () is disposed in the N-type heavily doped region (). An inward recessed shallow pit () with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (). By disposing the carrier enhancement region (), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit () can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

Insulated gate bipolar transistor and manufacturing method therefor

A semiconductor rectifying device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a filling structure, an upper electrode, a guard ring, and a guard layer. The epitaxial layer defines a plurality of trenches thereon. The filling structure includes an insulating material formed on the inner surface of the trench and a conductive material filled in the trench. A doped region of a second conductivity type is formed in the surface of the epitaxial layer between the filling structures. A method of manufacturing a semiconductor rectifying device includes forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, defining a plurality of trenches on the epitaxial layer, forming a plurality of filling structures in the plurality of trenches, and forming a doped region in the epitaxial layer between the filling structures.

Semiconductor rectifier and manufacturing method thereof

An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate () of a first conductive type, which is provided with a first major surface (S) and a second major surface (S), wherein the semiconductor substrate () comprises a primitive cell area () and a terminal protection area () which is located outside the primitive cell area; a first semiconductor layer () of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (), wherein the doping concentration of the first semiconductor layer () is higher than the doping concentration of the semiconductor substrate (); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer () in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed. Compared with the prior art, the present invention not only can improve the voltage resistance reliability of the insulted gate bipolar transistor, but also can reduce the forward conductive voltage drop of the insulated gate bipolar transistor.

A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.

Manufacturing method for reverse conducting insulated gate bipolar transistor

A reverse conducting insulated gate bipolar transistor (IGBT) manufacturing method, comprising the following steps: providing a substrate having an IGBT structure formed on the front surface thereof; implanting P+ ions onto the back surface of the substrate; forming a channel on the back surface of the substrate through photolithography and etching processes; planarizing the back surface of the substrate through a laser scanning process to form P-type and N-type interval structures; and forming a back surface collector by conducting a back metalizing process on the back surface of the substrate. Laser scanning process can process only the back surface structure requiring annealing, thus solve the problem of the front surface structure of the reverse conducting IGBT restricting back surface annealing to a low temperature, improving the P-type and N-type impurity activation efficiency in the back surface structure of the reverse conducting IGBT, and enhancing the performance of the reverse conducting IGBT.

Reverse conduction insulated gate bipolar transistor (IGBT) manufacturing method

An insulated gate bipolar transistor (IGBT) manufacturing method comprises the following steps: providing a semiconductor substrate of a first conducting type, the semiconductor substrate having a first major surface and a second major surface (); forming a field-stop layer of a second conducting type on the first major surface of the semiconductor substrate (); growing an oxide layer on the field-stop layer (); removing the oxide layer from the field-stop layer (); forming an epitaxial layer on the field-stop layer from which the oxide layer has been removed; and then manufacturing an IGBT on the epitaxial layer (). Before regular manufacturing of an IGBT, the surface defects of a substrate material are eliminated as many as possible before epitaxy is formed, and the quality of an epitaxial layer is improved, thereby improving the quality of the whole IGBT.

IGBT manufacturing method

Disclosed is a method for removing a polysilicon protection layer () on a back face of an IGBT having a field stop structure (). The method comprises thermally oxidizing the polysilicon protection layer () on the back face of the IGBT until the oxidation is terminated on a gate oxide layer () located above the polysilicon protection layer () to form a silicon dioxide layer (), and removing the formed silicon dioxide layer () and the gate oxide layer () by a dry etching process. The method for removing the protection layer is easier to control.

Method for removing polysilicon protection layer on a back face of an IGBT having a field stop structure

An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate () of the first conduction type which has a first major surface (S) and a second major surface (S), wherein the semiconductor substrate () comprises an active region () and a terminal protection area () which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (S) of the active region (), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers () of the first conduction type and second semiconductor layers () of the second conduction type of the active region, which are formed at the side of the second major surface (S) of the semiconductor substrate () alternately, wherein the IGBT only comprises the second semiconductor layers () in the terminal protection area () which is located at the side of the second major surface (S) of the semiconductor substrate ().

IGBT with built-in diode and manufacturing method therefor

A method for manufacturing an insulated gate bipolar transistor () comprises: providing a substrate (), forming a field oxide layer () on a front surface of the substrate (), and forming a terminal protection ring (); performing photoetching and etching on the active region field oxide layer () by using an active region photomask, introducing N-type ions into the substrate () by using a photoresist as a mask film; depositing and forming a polysilicon gate () on the etched substrate () of the field oxide layer (), and forming a protection layer on the polysilicon gate (); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.

Method for manufacturing insulated gate bipolar transistor

A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate () is provided; a p-type doped layer () is formed on the n-type substrate (); a hard layer () is formed on the p-type doped layer (); a groove () extending to the n-type substrate () is formed by etching on the p-type doped layer (); an n-type doped layer () is formed on the sidewalls and bottom of the groove (); the hard layer () is removed; p-type impurities of the p-type doped layer () and n-type impurities of the n-type doped layer () are driven in together, where the p-type impurities are diffused to form a p-type base region (), and the n-type impurities are diffused to form an n-type buffer layer (); a gated oxide dielectric layer () is formed on the surface of the groove (); and, a polysilicon layer () is deposited in the groove having formed therein the gate oxide dielectric layer (). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer () and the n-type doped layer () are driven in together to form the p-type base region () and the n-type buffer layer (), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.

Method for manufacturing injection-enhanced insulated-gate bipolar transistor

A method for preparing a power diode, including: providing a substrate (), growing a N type layer () on the front surface of the substrate (); forming a terminal protecting ring; forming an oxide layer (), knot-pushing to the terminal protecting ring; forming a gate oxide layer (), depositing a poly-silicon layer () on the gate oxide layer (); depositing a SiOlayer () on the surface of the poly-silicon layer () and a oxide layer (); forming a N type heavy doped region (); forming a P+ region; removing a photoresist, implanting P type ions using the SiOlayer () as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (), the gate oxide layer () being etched, and removing the SiOlayer (); and processing a front surface metallization and a back surface metallization treatment. According to the method for preparing the power diode, by adjusting the isotropy etching level of the SiOlayer and the ion implanting dose and energy, the threshold voltage of a DMOS structure can be adjusted, and the adjustment of the forward voltage drop for the device can be achieved.

Method for preparing power diode

A preparation method for a power diode, comprising: providing a substrate (), the substrate () having a front surface and a back surface opposite to the front surface, an N-type layer () growing on the front surface of the substrate (), and the N-type layer () having a first surface deviating from the substrate (); forming a terminal protection ring (); forming an oxide layer (), and performing knot pushing on the terminal protection ring (); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer () of the active region, and forming a gate oxide layer () on the first surface of the N-type layer () of the active region; depositing on the gate oxide layer () to form a polysilicon layer (); conducting photoetching using a polysilicon photoetching plate, taking a photoresist () as a mask layer to inject P-type ions into the N-type layer (), and forming a P-type body region () beneath the polysilicon layer () through ion scattering; forming an N-type heavily doped region; forming a P+region; conducting thermal annealing, activating injected impurities and removing the photoresist (); and conducting metallization processing on the first surface and the back surface of the substrate ().

Preparation method for power diode

A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure () and an active region (). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (), one surface of the electric field stop layer () departing from the underlayment is provided with a back-surface P-type structure (), and the surface of the back-surface P-type structure () is provided with a back-surface metal layer (). A plurality of polysilicon filling structures () which penetrate into the electric field stop layer () from the back-surface P-type structure () are formed in the active region ().

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Wuxi New District, China

Xiaoshe Deng