No. 24 Research Institute of China Electronics Technology Group Corporation

Chongqing Gigachip Technology Co. Ltd.

Crsc Research & Design Institute Group Co., Ltd.

Xiaoquan Yu

Zhiqiang Chen

Wanqiang Zhang

Dongbing Fu

Guangbing Chen

Jian'an Wang

Yuxin Wang

Daiguo Xu

Tao Liu

Hequan Jiang

Shiliu Xu

Xueliang Xu

Wenhui Zhang

Li Zhao

Hanyu Liu

Zongqi Xu

Chaopeng Yue

Lihua Chen

Xiaoling Su

Wenhua Yao

Hongfei Liu

Yingfeng Xie

Shize Xu

Jia Huang

Ming Jiang

The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

High-speed digital logic circuit for SAR_ADC and sampling adjustment method

Growing community of inventors

Chongqing, China

Xiaoquan Yu