Integrated Device Technology, Inc.

Synaptics Corporation

Xiaoqian Zhang

Shubing Zhai

Qi Li

Zhiyong Guan

Sibing Wang

Yanbo Wang

Zhonghai Gan

Jing Qian

Henry Zeng

Lu Yang

Xuexin Liu

Yefei Sun

The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.

Stream clock recovery in high definition multimedia digital system

A multi-monitor display driver that provides consolidated EDID data is provided. The display driver reads the EDID data from the one or more monitors coupled to the driver, determines a consolidated EDID data that is compatible with each of the monitors, and writes the EDID data to an EDID memory in the driver. A source interacting with the driver reads the consolidated EDID data to control interactions with the driver.

Dynamic EDID generation

A method of transmitting audio data across a digital interface is provided. The method includes receiving audio data, organized as a plurality of audio samples. At least one of the plurality of audio samples may be placed into a data packet. The data packet may be transmitted during a valid transmission interval if the data packet is full or during a valid transmission interval in response to receiving a packet send event.

Managing transmit jitter for multi-format digital audio transmission

A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

Method and circuit for DisplayPort video clock recovery

A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O peripheral to be accessed, disabling the operation of the CPU and synchronizing a memory from the CPU clock domain to the clock domain of the identified I/O peripheral. Upon completion of the read/write access, the identified I/O peripheral sends an acknowledgment, the memory is then synchronized from the clock domain of the I/O peripheral to the CPU clock domain and the operation of the CPU is then enabled. In another embodiment, if the acknowledgement from the identified I/O peripheral is not received within a predefined time duration, reserved data is sent to the CPU and the operation/access can be restarted.

Method for synchronization of peripherals with a central processing unit in an embedded system

A biphase mark signal receiver includes a data and clock recovery circuit. The data recovery circuit may include a coarse recovery stage and a fine recovery stage. The coarse recovery stage is configured to detect repeating occurrences of a first preamble (e.g., Y-preamble) within a biphase encoded data stream received by the data recovery circuit. The fine recovery stage is configured to generate a recovered data stream, in response to estimating a plurality of timing decision points (e.g., 3UI, 2UI and 1UI) from the repeating occurrences of the first preamble detected by the coarse recovery stage.

Asynchronous biphase mark signal receivers and methods of operating same

Data received from a bursty interface is received on a burst-by-burst basis. Once a burst is received, it is stored in a processing queue. A complete burst is received so long a processing queue can accommodate a data burst. The complete data burst is directed to an output and used to create a complete data burst on said output. The output burst is dispatched so long as a receiving port is able to accept the output burst.

Method and apparatus for forwarding bursty data

A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

Phase-locked loop

A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.

Method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a system packet interface device

A data output circuit includes a plurality of clocked data output buffers, each of which drives a data output thereof responsive to a clock signal and an adjustable multiphase clock signal generator that generates a plurality of clock signals of different phases and that is operative to shift the plurality of clock signals relative to a reference clock signal responsive to a first control signal. The data output circuit further includes a clock signal selector that selectively applies the plurality of clock signals to the data output buffers responsive to a second control signal. The adjustable multiphase clock signal generator may include, for example, a control loop, such as a phase locked loop or a delay locked loop, which selectively feeds back one of the plurality of clock signals responsive to the first control signal. The clock signal selector may include a plurality of clock signal selectors, respective ones of which receive the plurality of clock signals and selectively apply the plurality of clock signals to respective ones of the data output buffers responsive to the second control signal.

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Shanghai, China

Xiaoqian Zhang