Intel Corporation

Xiaoqian Li

Omkar G Karhade

Nitin A Deshpande

Divya Pratap

Debendra Mallik

Srinivas V Pietambaram

Ravindranath Vithal Mahajan

Zhichao Zhang

Sujit Sharan

William J Lambert

Brandon C Marin

Jeremy D Ecton

Mitul Bharat Modi

Tarek A Ibrahim

Bai Nie

Bharat P Penmecha

Wesley Brook Morgan

Kemal Aygün

Suresh V Pothukuchi

Robert L Sankman

Chia-Pin Chiu

Kristof Darmawikarta

Rahul N Manepalli

James E Jaussi

Robert Alan May

Sri Ranga Sai Boyapati

Gang Duan

Sidharth Dalmia

Sai Vadlamani

Hiroki Tanaka

Srikant Nekkanty

Jimin Yao

Gregorio R Murtagian

Yiqun Bai

Jason M Gamba

Sameer Paital

Arnab Sarkar

Todd R Coons

Zhenguo Jiang

Asako Toda

Kaveh Hosseini

Kenneth Brown

Jing Fang

Wei Li

Jingyi Huang

Kumar Abhishek Singh

Shamsul Abedin

Rajesh Inti

Stephen Smith

Susheel Jadhav

Srichaitra Chavali

Kevin P Ma

Conor O'keeffe

Casey Thielen

Santosh Shaw

Marely E Tejeda Ferrari

Thu Ngoc Tran

Omkar Karhade

Yew Fatt Kok

Nitin Deshpande

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

High bandwidth optical interconnection architectures

Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Faraday rotator interconnect as a through-via configuration in a patch architecture

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active side and an opposing backside, and wherein the PIC is embedded in the insulating material with the active side facing down; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the backside of the PIC and the conductive pillar; and an optical component optically coupled to the active surface of the PIC.

Photonic integrated circuit packaging architectures

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package includes a photonics die and a plurality of v-grooves on the photonics die. A barrier structure proximate the plurality of v-grooves.

Barriers for grooves in photonics dies

Embodiments described herein may be related to apparatuses, processes, and techniques for coupling a micro-lens array to a photonics die. In embodiments, this coupling may be performed as an attach at a wafer level. In embodiments, wafer level optical testing of the photonics die with the attached micro-lens array may be tested electrically and optically before the photonics die is assembled into a package, in various configurations. Other embodiments may be described and/or claimed.

Micro-lens array optically coupled with a photonics die

Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package comprises a photonics die and a plurality of v-grooves on the photonics die. In an embodiment, a lens array is optically coupled to a spot size converter on the photonics die. In an embodiment, the lens array comprises a main body and a plurality of lenses extending out from the main body.

Enabling passive alignment for lens attach

Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

Photonic integrated circuit packaging architecture

Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.

Package expanded beam connector for on-package optics

Embodiments described herein may be related to apparatuses, processes, and techniques related to a bidirectional optical grating coupler that may be used for testing. A photonic apparatus includes a first layer with electro-optical circuitry that is optically coupled with a bidirectional optical grating coupler. A second layer is physically coupled with a first side of the first layer and includes a first light path to optically coupled with the bidirectional optical grating coupler. A third layer is physically coupled with a second side of the first layer opposite the first side of the first layer, and includes a second light path that optically couples with the bidirectional grating coupler. Operational testing of the electro-optical circuitry is based in part on light received or transmitted through the second light path. Other embodiments may be described and/or claimed.

Bidirectional optical grating coupler with multiple light paths for testing photonics devices

Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

Optical multichip package with multiple system-on-chip dies

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, where the package substrate comprises a recessed edge. In an embodiment, a compute die is on the package substrate, and an optics die on the package substrate and overhanging the recessed edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the optics die. In an embodiment, a lid covers the recess in the package substrate.

Completely encapsulated optical multi chip package

A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.

Patch on interposer architecture for low cost optical co-packaging

A groove alignment structure comprises an etch stop material and a substrate over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of the optical fibers extends above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.

Silicon groove architectures and manufacturing processes for passive alignment in a photonics die

Growing community of inventors

Chandler, AZ, United States of America

Xiaoqian Li