Silergy Semiconductor Technology (hangzhou) Ltd

Xiaoping Chen

Hongfeng Fan

Jaime Tseng

A clock dividing frequency circuit can include: a controlled current source configured to generate a driving current that varies with a dividing frequency control signal; a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to the driving current, where the ramp signal is reset according to pulses of a dividing frequency clock signal; and a dividing frequency pulse generating circuit configured to generate the dividing frequency clock signal by a dividing frequency operation according to the ramp signal and a system clock signal.

Clock dividing frequency circuit, control circuit and power management integrated circuit

A control circuit for generating a switching control signal to control switching operations of a power switch in a power stage circuit, can include: a first control loop configured to receive a first voltage feedback signal, and to generate a first compensation signal; a voltage regulating circuit configured to receive an output voltage signal of the power stage circuit, and to generate a second compensation signal according to a difference between an output voltage signal of the power stage circuit during different time periods; and control and driving circuit configured to receive the first and second compensation signals and a sense voltage signal that represents a current through an inductor of the power stage circuit, and to generate an OFF signal, and a switching control signal according to the OFF signal and an ON signal.

Growing community of inventors

Hangzhou, China

Xiaoping Chen