Infineon Technologies Ag

Intel Corporation

Apple Inc.

Siemens Aktiengesellschaft

Lantiq Beteiligungs Gmbh & Co. Kg

Intel Mobile Communications Gmbh

Micronas Gmbh

Infineon Technologies LLC

Intel Germany Gmbh & Co. Kg

Xiaoning Nie

Jinan Lin

Lajos Gazsi

Dirk Wendel

Thomas Wahl

Soenke Mehrgardt

Maik Brett

Lorenzo Di Gregorio

Ulrich Leucht-Roth

Christian Jenkner

Tideya Kella

Siegmar Koeppe

Mathias Kohlenz

Tilman Giese

Ralf Itjeshorst

Peter Hober

S&ouml;nke Mehrgardt

Sankar Narayan Jagannathan

Ulf Nordqvist

Sankamarayan Jagannathan

Stefan Maier

Claudia Mayr

Jin-Soo Yoo

Xianming Deng

Denny Brem

Klaus Mott

The present disclosure describes a system including a data storage device coupled to and shared by first and second processing devices and controlled by a data access controller. The data access controller can receive a data access request from the first processing device to access a first number of data storage units of the data storage device. A current storage unit count represents a second number of data storage units occupied in the data storage device. The data access controller can determine an updated storage unit count based on the current storage unit count and the first number of data storage units. In response to the updated storage unit count being below an upper threshold value and above a lower threshold value, the data access controller can grant the data access request to access the first number of data storage units of the data storage device.

Data access control for dataflow computing systems

A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.

Parallel merge sorter circuit

According to one embodiment, a connection is established between a first communication device and a second communication device in accordance with one or more communication layers. Each communication layer is associated with a standard structure and protocol. An ad hoc communication layer structure and/or protocol are determined at the first communication device. The ad hoc communication layer structure and/or protocol are communicated to the second communication device. One or more of the standard structures and/or protocols are replaced at the first communication device with the ad hoc communication layer structure and/or protocol responsive to the second communication device acknowledging acceptance of the ad hoc communication layer structure and/or protocol.

Ad hoc communication protocol method and apparatus

The disclosure relates to a data processing device, comprising: a processing element configured to process a plurality of data packets according to a communication protocol to provide a plurality of processed data packets each comprising a first part and a second part; and an interface configured to offload the second parts of the plurality of processed data packets to a remote data processing device and configured to notify the remote processing device of the offload of the second parts of the plurality of processed data packets.

Data processing device and method for offloading data to remote data processing device

A data moving processor includes a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.

Data moving processor

A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.

Data transfer in a computing device

In order to be able to use a smaller routing table () and, thus, to reduce the costs and power consumption and to improve the performance of an IP router, it is proposed to extract a destination address identifier (ADR) from a data packet to be forwarded by the IP router, compress the extracted destination address identifier (ADR) by using a lossless data compression algorithm, and compare the compressed destination address identifier with entries stored in the routing table () so as to find a correspondence between the destination address identifier and one of the entries of the routing table (). Each entry of the routing table () corresponds to a possible or available forwarding address of the IP router, the forwarding addresses having been compressed with the same data compression algorithm as the destination address identifier. After having found a correspondence between the destination address identifier and one of the compressed forwarding addresses stored in the routing table (), a switch () of the IP router switches the respective data packet to one of its output links (OUT) which is associated with the respective forwarding address matching the destination address identifier (ADR).

Method for routing of data packets and routing apparatus

An arrangement and a method for processing data of multiprotocol data packets comprises at least one multiplexer connected to input ports; at least one first programmable data processing unit configured to provide header words and into payload words; a buffer management unit configured to generate localization data which specifies a corresponding memory area of the payload memory; a descriptor generator unit for generating data packet descriptors; a RISC processor configured to generate, in dependence on the data packet descriptors, header data for transmit data packets and payload processing instructions for processing data of the data packet payload words, stored in the payload memory, of the associated received data packet; and at least one second programmable data processing unit configured to process the payload words from the payload memory in accordance with the payload processing instructions and assembles the payload words with the header data to form transmit data packets.

Multichannel processor

The present invention relates to a parallel multithread processor () with split contexts, with M parallel-connected standard processor root units () being provided for instruction execution of program instructions for different threads (T), and with N context memories () being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit () being provided, by means of which each standard processor root unit () can be connected to each context memory (). The invention accordingly provides a processor architecture in which a number N of different context memories () and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (). This means that use is made not only of paralleling of the standard processor root units (), but also of the threads (T) and of the context memories ().

Parallel multithread processor (PMT) with split contexts

In a method for forwarding data packets in a network a circuit comprises a data storage and a control device. Each data packet has a destination address and the data storage comprises T data sub-storages for storing all network addresses which are coded by a particular coding method on the basis of their respective key bit length in precisely one of the data sub-storages. The t-th data sub-storage is divided into blocks having D data elements of identical data element bit length, where t&#x3b5;[1, . . . , T] and D is the smallest common multiple of t&#x3b5;[1, . . . , T]. The control device receives data packets, each having a destination address, codes a destination address of a received data packet using the particular coding method to produce a coded key, and compares the coded key on the basis of its key bit length with the coded addresses stored in the corresponding data sub-store block by block in order to forward the respective data packet via an output to the destination address whose associated coded address matches the coded key from the respective received data packet.

Circuit and a method for forwarding data packets in a network

A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is read with a first bit length from a first bit field in the first memory unit starting at a first start point. The bit segment that has been read is stored in the first bit field in the second memory unit starting at a second start point. The first or the second start points is updated by a predetermined value and the updated start point is stored for subsequent method steps.

Method and programmable unit for bit field shifting

A unit for distributing and processing data packets has an administration unit for distributing the data packets to parallel-connected processor units. In this case, the processors of adjacent processor units have intermediate connections for interchanging data. The administration unit distributes the data packets in dependence on administration information for the data packets and/or on operating information for the processor units.

Growing community of inventors

Neubiberg, Germany

Xiaoning Nie