Mindspeed Technologies, Inc.

Conexant Systems, Inc.

Newport Fab, LLC

Xiaoming Li

Surinderjit S Dhaliwal

Eugene Robert Worley

Kevin Q Yin

Mark R Tennyson

Umesh Sharma

Suryanarayana Shivakumar Bhattacharya

Hong J Wu

Mishel Matioubian

There is provided a method of scheduler assisted power management for semiconductor devices. By accessing and analyzing workload data for tasks to be completed, a scheduler may provide finer grained control for determining and implementing an efficient power management policy. In this manner, tasks with completion deadlines can be allocated sufficient resources without wasteful power consumption resulting from ramping up of performance through overestimating of voltage or frequency increases. Additionally, power management may be planned for longer periods, rather than looking only at immediate data to be processed and constantly fluctuating voltage and frequency. In this manner, power management can run more smoothly and efficiently compared to conventional means of power management that ignore data from a scheduler when determining power management policy.

Scheduler with voltage management

There is provided a semiconductor package configured for externally controlled power management. Instead of integrating voltage regulation on-chip as done conventionally, power regulation is moved externally to the PCB level, providing numerous package advantages including size, simplicity, power efficiency, integration flexibility, and thermal dissipation. In particular, the use of flip-chip package configurations provides ready access to power supply bumps, which also allows the use of a universal receiving PCB and power supply through simple reconfiguring of voltage traces. As a result, flexible power management can be implemented, and portions of semiconductor packages may be managed for performance or thermal considerations, which may be of particular use for applications such as multi-core processors.

System on chip power management through package configuration

There is provided a semiconductor package that includes a first semiconductor die mounted on a package substrate. The semiconductor package further includes a second semiconductor die mounted on the first semiconductor die and including a thermal sensing and reset protection circuit. The thermal sensing and reset protection circuit is configured to determine a temperature of the first semiconductor die and to provide a reset protection signal to the first semiconductor die when the temperature of the first semiconductor die is substantially equal to a preset temperature so as to protect the first semiconductor die from thermal runaway. The reset protection signal can cause the first semiconductor die to be in a sleep mode or a reset state.

Thermal sensing and reset protection for an integrated circuit chip

An electrostatic discharge (ESD) protection circuit includes an NPN transistor having a collector terminal connected to a voltage source and an emitter terminal connected to the ground via a diode. The NPN transistor includes a base terminal for receiving a base current to turn on the NPN transistor to allow an electrostatic discharge at the voltage source to flow through the NPN transistor to the ground. The ESD protection circuit further includes a PMOS transistor having a source terminal coupled to the voltage source and a drain terminal coupled to the base terminal of the NPN transistor. The PMOS transistor includes a gate terminal for receiving a first and a second gate voltage. The ESD protection circuit further includes an R-C circuit coupled between the source voltage and the ground. The R-C circuit is configured to supply the first gate voltage to the PMOS transistor when there is no electrostatic discharge to turn off the PMOS transistor and the second gate voltage responsive to the electrostatic discharge to turn on the PMOS transistor for a predetermined time period. The ESD protection circuit further includes a voltage divider circuit coupled between the voltage source and the ground and coupled to the R-C circuit.

High voltage tolerant electrostatic discharge protection circuit

An anti-reflective coating for use in the fabrication of a semiconductor device includes a thin oxide layer and an overlying layer of silicon oxynitride. The anti-reflective layer is advantageously used in the fabrication of FLASH memory devices which include a layer of polycrystalline silicon and an underlying layer of silicon nitride. After being used to pattern the polycrystalline silicon and silicon nitride, the anti-reflective coating is removed in a solution of hot phosphoric acid with the removal taking place before the silicon oxynitride is exposed to any elevated temperatures.

Anti-reflective coating and process using an anti-reflective coating

An electrostatic discharge (ESD) protection circuit comprises a P-channel field effect transistor (PFET), a buffer and a damping network to provide improved protection for an integrated circuit against high-voltage ESD pulses. The ESD protection circuit is capable of being fabricated with a reduced surface area layout to be fully synthesisable with the integrated circuit which it is designed to protect.

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Irvine, CA, United States of America

Xiaoming Li