Hitachi, Ltd.

Xiaoming Jiang

Satoshi Yagi

Ikuya Yagisawa

Azuma Kano

Junichi Iida

Katsuyoshi Suzuki

Akihiro Inamura

Taro Takahashi

Daisuke Mitsutake

Kenichi Ozaki

Daisuke Mitsutaka

A disk array apparatus capable of reducing a disk drive fault rate where a time-out failure has occurred. The disk array apparatus includes a plurality of disk drives, and a control unit for performing data input/output processing of the disk drives in response to a data input/output request from a host system. The control unit includes: a memory for storing control information for specifying a failure of at least one of the disk drives, and failure information of the faulty disk drive, a circuit for specifying, from the failure information, the disk drive in which a time-out failure has occurred, and issuing an instruction to retry a control command to the disk drive, and a circuit for outputting a control signal to the faulty disk drive in order to hard reset the disk drive if the disk drive does not recover from the failure.

Disk array apparatus and method for controlling the same

An I/O processor determines whether or not the amount of dirty data on a cache memory exceeds a threshold value and, if the determination is that this threshold value has been exceeded, writes a portion of the dirty data of the cache memory to a storage device. If a power source monitoring and control unit detects a voltage abnormality of the supplied power, the power monitoring and control unit maintains supply of power using power from a battery, so that a processor receives supply of power from the battery and saves the dirty data stored on the cache memory to a non-volatile memory.

Storage control unit and data management method

Flushing cached data upon power interruption

A storage system includes: a flash disk having a plurality of flash memory units; a management table for hierarchically managing the write life of each flash memory unit on a specified storage area basis; and a controller for hierarchically distributing write-processing to the flash memory according to the management table.

Storage system and write distribution method

In a storage system including a plurality of data controllers that receive a data input/output request that is input via an external communication path and perform data input/output processing with respect to a storage resource in response to this request, the plurality of data controllers being connected by a data communication path and being able to communicate with one another, if a data input/output request has been input into one of the controllers, the plurality of data controllers and shares execution of the data input/output processing by communication through the data communication path.

System and method for storage system

The invention verifies the validity of instructions transmitted between controllers without complicating the structure of the electrical connection between controllers. The initial setup detection unit detects whether an initial setup of the lower communications network has been completed. When a fault in the path to the storage unit has been detected by the fault detection unit, the switching request output unit outputs a switching request signal to the switching permission unit. When the preparation status detection unit is aware that the lower communications network has completed initial setup, the preparation status detection unit outputs the preparation complete signal to the switching permission unit. When both the switching request signal and the preparation complete signal are input, the switching permission unit outputs the switching signal to the path switching unit. The path switching unit switches the path in accordance with the signal from the switching permission unit.

Storage control device and storage control device path switching method

Each of controllers includes: a transistor; a data processor for executing predetermined data processing and turning the transistor on or off in accordance with the data processing result; a pull-up resistor connected to an output terminal of the transistor; and a level separating resistor connected to the output terminal of the transistor, and the data processor of each controller detects a signal level of a control signal output from the output terminal of the transistor and judges whether or not any defect has occurred in its own controller, based on the detection result.

Control apparatus and control method

Each disk enclosurecontains an ENC bypassA for a disk connectorA, and PBCA andA, which perform selective switching to transfer data via either the disk connectorA or the ENC bypassA. When the occurrence of an anomaly in the disk connectorA is detected, the CTLA connected to the disk connectorA asks the CTLB to bypass the disk connectorA, whereupon the CTLB switches the data communication path from the disk connectorA to the ENC bypassA by controlling the PBCA andA.

Storage control system and operating method for storage control system

In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably connected to the cache memory via a plurality of data buses, when receiving a request for access to the cache memory from any one of the CPU, the channel control units and the disk control units, the data transfer integrated circuit provides access to the cache memory by use of a certain number of one or ones of the data buses, which number is determinable in accordance with a transfer data length that is set in the access request.

Disk array device with utilization of a dual-bus architecture dependent on data length of cache access requests

When only one type of a memory having an access rate necessary for high-speed data processing is equipped with a subsystem so as to accommodate the entire amount of storage required for the subsystem, a considerable rise in costs occurs. Therefore, in order to keep the rise in cost to a minimum, high-speed memory of a storage capacity required for the high-speed processing and low-speed memory of a storage capacity that can be safely employed for low-speed processing are both equipped with the disk memory system. With this arrangement, the rise in costs can be kept to a minimum, and access time to the memory can be reduced. The performance of the disk memory system can be thereby improved.

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Odawara, Japan

Xiaoming Jiang