Qualcomm Incorporated

Xiaoming Chen

Ryan David Lane

Xiaonan Zhang

Darryl Sheldon Jessie

Young Kyu Song

Aristotele Hadjichristos

Rajneesh Kumar

Yue Li

Babak Nejati

Jaehyun Yeon

Li-Sheng Weng

Suhyung Hwang

Charles David Paynter

Yunseo Park

Zhongping Bao

Jeahyeong Han

Chaoqi Zhang

Jack Monjay Yao

Certain aspects of the present disclosure generally relate to a circuit board with ground vias offset from associated ground bumps. One example circuit board generally includes a first signal connection terminal configured to connect a signal line of the circuit board to an integrated circuit (IC); a ground plane having a first ground connection terminal disposed adjacent to the first signal connection terminal, the first ground connection terminal being configured to provide a ground connection between the ground plane and the IC; and a first ground via associated with and disposed adjacent to the first ground connection terminal and coupled to the ground plane, wherein, from an overhead view of the circuit board, the first ground via is located at a position that is offset from a first axis on which the first signal connection terminal and the first ground connection terminal are disposed.

Electromagnetic (EM) field rotation for interconnection between chip and circuit board

A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

Package comprising a substrate having a via wall configured as a shield

Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

DC/ AC dual function Power Delivery Network (PDN) decoupling capacitor

Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

High quality factor inductor implemented in wafer level packaging (WLP)

In designing an integrated circuit on a die having a set of die bumps, a method to generate a set of lumped circuit parameter values associated with the set of die bumps, based upon distances between the set of die bumps and the center of the die, the method also based upon a sample-data distribution function of a die bump distance variable and a sample-data distribution function of a lumped circuit parameter variable. Other embodiments are described and claimed.

Statistical integrated circuit package modeling for analysis at the early design age

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San Diego, CA, United States of America

Xiaoming Chen