Intel Corporation

Baoshan Iron & Steel Co., Ltd.

Other

Corning Incorporated

Delta Electronics (shanghai) Co., Ltd

Shanghai Mechanized Construction Group Co., Ltd.

Xiaoming Chen

Anbang Yao

Ping Tak Tang

Joydeep Ray

Altug Koker

Michael S Strickland

Abhishek R Appu

Tatiana Shpeisman

Elmoustapha Ould-Ahmed-Vall

Rajkishore Barik

Feng Chen

Dukhwan Kim

Eriko Nurvitadhi

Kevin Nealis

Balaji Vembu

Mike B Macpherson

Linda L Hurd

Sara S Baghsorkhi

Kamal Sinha

Nicolas C Galoppo Von Borries

Nadathur Rajagopalan Satish

Tsung-Han Lin

Liwei Ma

Farshad Akhbari

Narayan Srinivasa

John Charles Weast

Ben J Ashbaugh

Vasanth Ranganathan

Sanjeev S Jahagirdar

Sanu K Mathew

Justin E Gottschlich

Mark A Anders

Himanshu Kaul

Brian T Lewis

Prasoonkumar Surti

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Mike MacPherson

Yang Liu

Chandrasekaran Sakthivel

Travis T Schluessler

Ankur N Shah

Liang Ma

Barath Lakshmanan

Jeremy Bottleson

Murali Sundaresan

Dhawal Srivastava

Jeffrey R Jackson

Sherine Abdelhak

Jingyi Jin

Sachin B Godse

Shanqing Li

Leonard Truong

Jonathan Kennedy

Hongyang Wu

Cheng Lu

Shandong Wang

Yun Gang Li

Ming Lu

Bing Zhang

Zhi Liu

Kangjian Wang

Xun Liu

Yan Hao

Tao Zheng

Yikai Wang

Peilei Qu

Xiaofeng Wu

Junjie Huang

Jizhe Quan

Jun Ding

Feiqin Hao

Yan Ke

Zhiming Wang

Tao Ge

Ming Gong

Anhang Yao

Yuanke Luo

Tao Lv

Zhiqiao Zheng

Limin Shang

Hua Ye

Kaifu Yang

Jingyu Huang

Baorong Jia

Jiqing Li

Xinzhi Wu

Fanquan Meng

Linfeng Sheng

Zhiyong Zhan

Shifen Yan

Xiaoyun Qiu

Jiale Xu

Liangfeng Xia

Jieyun Zhu

One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

Compute optimizations for neural networks

Described herein is a general-purpose graphics processing unit including a multiprocessor having a single instruction, multiple thread, SIMT, architecture. The multiprocessor comprises multiple sets of compute units each having a first logic unit configured to perform floating-point operations and a second logic unit configured to perform integer operations, with a thread of the floating-point instruction being executed in parallel with a thread of the integer instruction.

Multicore processor with each core having independent floating point datapath and integer datapath

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

A mechanism is described for facilitating efficient training of neural networks at computing devices. A method of embodiments, as described herein, includes detecting one or more inputs for training of a neural network, and introducing randomness in floating point (FP) numbers to prevent overtraining of the neural network, where introducing randomness includes replacing less-significant low-order bits of operand and result values with new low-order bits during the training of the neural network.

Training with adaptive runtime and precision profiling

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Instructions and logic to perform floating point and integer operations for machine learning

One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

Concurrent multi-datatype execution within a processing resource

One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

Compute optimization mechanism

One embodiment provides for a general-purpose graphics processing unit including a scheduler to schedule multiple matrix operations for execution by a general-purpose graphics processing unit. The multiple matrix operations are determined based on a single machine learning compute instruction. The single machine learning compute instruction is a convolution instruction and the multiple matrix operations are associated with a convolution operation.

Specialized fixed function hardware for efficient convolution

A library of machine learning primitives is provided to optimize a machine learning model to improve the efficiency of inference operations. In one embodiment a trained convolutional neural network (CNN) model is processed into a trained CNN model via pruning, convolution window optimization, and quantization.

Convolutional neural network optimization mechanism

A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine an optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Tool for facilitating efficiency in machine learning

Growing community of inventors

Shanghai, China

Xiaoming Chen