Lsi Corporation

Nxp Usa, Inc.

Xiaomin Lu

Franciscus Petrus Widdershoven

Paul Kimelman

Brian Christopher Kahne

Adam Fuks

A scalable neural network accelerator may include a first circuit for selecting a sub array of an array of registers, wherein the sub array comprises LH rows of registers and LW columns of registers, and wherein LH and RH are integers. The accelerator may also include a register for storing a value that determines LH. In addition, the accelerator may include a first load circuit for loading data received from the memory bus into registers of the sub array.

Scalable neural network accelerator architecture

In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments of the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Iterative-division operations such as for header compression in packet-based communications

In one embodiment of a header-compression method, a timestamp value is divided by a stride value using a plurality of binary-shift operations corresponding to a Taylor expansion series of the reciprocal stride value in a base of &#xbd;. When the division-logic circuitry of an arithmetic logic unit in the corresponding communication device is not designed to handle operands that can accommodate the length of the timestamp and/or stride values, the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

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Austin, TX, United States of America

Xiaomin Lu