Taiwan Semiconductor Manufacturing Comp. Ltd.

Xiaomeng Chen

Chia-Shiung Tsai

Ping-Yin Liu

Yeur-Luen Tu

Shih-Chang Liu

Chen-Jong Wang

Lan-Lin Chao

Chern-Yow Hsu

Chung-Yi Yu

Xin-Hua Huang

Chi-Ming Chen

Po-Chun Liu

Hsun-Chung Kuang

Chen-Hao Chiang

Yen-Chang Chu

Chih-Ming Chen

Cheng-Ta Wu

Szu-Yu Wang

Chien-Huei Chen

Hung-Yi Chung

Chih-Hui Huang

Hung-Hua Lin

Zhiqiang Wu

Yuan-Chih Hsieh

Yu-Hung Cheng

Shih-Chang Wang

Pin-Nan Tseng

Chien-Hong Chen

Cheng-Yuan Tsai

Ming Chyi Liu

Sheng-Chau Chen

Bruce C S Chou

Jung-Kuo Tu

Cheng-Tai Hsiao

Chun-Han Tsao

Yung-Cheng Lin

Cheng-Te Lee

Pei-Chao Su

Kuang-Shing Chen

Tsung-Te Chou

Wei-Chen Wu

Chan-Ming Chang

Shih-Yung Chen

Li-Jou Lee

Chien-An Lin

Szu-Ying Chen

Tsung-Yu Chen

Kai-Wen Cheng

Chih-Wen Hsiung

Han-Chin Chiu

Shu-Ju Tsai

Ming-Chang Ching

Xin-Chung Kuang

Jen-Cheng Liu

Hsing-Lien Lin

King-Yuen Wong

Chen-Fa Lu

Trinh Hai Dang

Cheng-Kuang Lee

Cheng-Jong Wang

Chao-Ting Hong

Teng-Cheng Hsu

Chia-Chiung Tsai

Hsiu-Hui Huang

A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Hot spot defect detecting method and hot spot defect detecting system

A method of qualifying semiconductor wafer processing includes: illuminating a semiconductor wafer simultaneously with source light having wavelengths in a plurality of wavebands, including at least a first waveband and a second waveband, the second waveband being different from the first waveband; separating light reflected from the semiconductor wafer as a result of said illuminating, the separating dividing the reflected light according to waveband; generating a first image of the semiconductor wafer based on reflected light separated into the first waveband; and, generating a second image of the semiconductor wafer base on reflected light separated into the second waveband.

Simultaneous multi-bandwidth optical inspection of semiconductor devices

A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

Dual facing BSI image sensors with wafer level stacking

A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Integrate rinse module in hybrid bonding platform

A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

Semiconductor arrangement with capacitor

A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.

Backside illuminated photo-sensitive device with gradated buffer layer

An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.

Wafer bonding method and apparatus with curved surfaces

A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.

Method for semiconductor wafer inspection and system thereof

A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

Semiconductor arrangement with capacitor and method of fabricating the same

A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.

Semiconductor arrangement having capacitor separated from active region

Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method

Growing community of inventors

Hsinchu, Taiwan

Xiaomeng Chen