Chinese Academy of Sciences

Xiaolong Ma

Huaxiang Yin

Huilong Zhu

Qiuxia Xu

Dapeng Chen

Changliang Qin

Qiang Xue

Zuozhen Fu

Houzhen Wei

Hang Ruan

Xiang Sun

Guilei Wang

Yong Wan

Sen Xu

Jiangshan Li

Weijia Xu

Qingqing Liang

Lei Liu

Yingyao Qin

Changliang Qi

The present disclosure relates to the field of rock soil detection and in particular to a multi-probe nuclear magnetic resonance (NMR) rock soil in-situ monitoring system, which includes a multi-probe component, a spectrograph component, an industrial control computer and a power cable. The multi-probe component includes a shell and multiple nuclear magnetic probes disposed inside the shell. The multiple nuclear magnetic probes are respectively located at the soil layers of different depths and have different measurement frequencies. The spectrograph component is used to transmit and receive NMR-measured radio frequency signals, the industrial control computer is used to transmit a measurement instruction and perform real-time processing on the measurement data, and the power cable is connected with the multiple nuclear magnetic probes, the spectrograph component and the industrial control computer to supply power and transmit the measurement data.

Multi-probe multi-frequency nuclear magnetic resonance rock soil in-situ monitoring system

The present disclosure relates to a static cone penetration test device. The device includes a housing, an optical window and a friction cylinder coaxially connected. Light sources are mounted in the optical window and a static cone penetration assembly is disposed in the friction cylinder to detect a resistance the device suffers when the device is pressed into soil. An optical fiber sensor, a wireless transceiver, a data processing chip and a power supply are disposed in the housing. The optical fiber sensor is used to receive the reflected light of a target object and output spatial position information and spectrum information. The wireless transceiver is used to upload test data and receive a control signal. The data processing chip is used to analyze the test data. The present disclosure has the advantages of compact structure, high spectral resolution, quick imaging speed, and strong immunity to interference.

Static cone penetration test device and test method incorporating hyperspectral imaging technology

The disclosure relates to a multi-probe NMR rock soil in-situ monitoring method, which includes: placing a multi-probe component to a target layer in a soil drill hole, where the multi-probe component includes NMR probes respectively located at the soils at different depths and having different measurement frequencies; performing in-situ NMR measurement on soils at different depths at the same time; by using a spectrometer component, receiving measurement signals from all NMR probes and performing frequency mapping analysis to distinguish NMR raw measurement data collected by each NMR probe; by using the spectrometer component, transmitting the raw measurement data to an industrial control computer to perform an inversion processing on the measurement data of the NMR probes and obtain T2 distribution mapping of the soils at different positions; based on the T2 distribution mapping, obtaining a water ratio of soil, a soil-water characteristics curve, soil non-homogeneity information and oil pollutant information.

Multi-probe nuclear magnetic resonance rock soil in-situ monitoring method

A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

Method of manufacturing MOS transistor with stack of cascaded nanowires

Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Method of manufacturing stacked nanowire MOS transistor

A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

Semiconductor device and manufacturing method therefor

The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

Semiconductor device and method of manufacturing the same

A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.

FinFET device and method for manufacturing the same

A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device comprises, including forming a plurality of fins on a substrate, forming, a dummy gate stack on the fins forming a gate spacer on opposite sides of the dummy gate stack, forming source/drain trenches by etching the fins with the gate spacer and the dummy gate stack as a mask, forming source/drain extension regions on the bottom and sides of the trenches by performing lightly-doping ion implantation; and by performing epitaxial growth in and/or on the source/drain trenches, removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Method for manufacturing semiconductor device including doping epitaxial source drain extension regions

The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Semiconductor structure and method for manufacturing the same

The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.

Semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region.

Growing community of inventors

Beijing, China

Xiaolong Ma