Axis Semiconductor, Inc.

Other

Axiowave Networks, Inc.

West Lane Data LLC

Rs Stata LLC

Xiaolin Wang

Qian Wu

Benjamin Marshall

Ajay C Mahagaokar

Ke Ning

Gregory Steve Pitarys

Fugui Wang

Jie Sun

Subhasis Pal

Satish Soman

Ray Rajib

Michael T Wright

Craig B Agricola

Stephen E Smith

Zachary Filan

Sijian Lin

John Eppling

Ben Marshall

Gregory Pitarys

A computing device includes a transport switch comprising read and write switches that provide switched circuit interconnections between input and output ports for simultaneous data communication between a plurality of memory clients and a plurality of memory banks, such as between cores of a multi-core processor simultaneously accessing L1, L2, and L3 memory banks. Embodiments implement switching designs that are derived from existing switched network architectures. Other embodiments implement a novel circuit switch design based on 8&#xd7;8 building blocks. The transport switch can be non-blocking, and can be self-routing. An additional switching layer can be included to provide port rearrangement for rearrangeable non-blocking switches. A transport compiler can be used to determine port-pair configurations of the switch. A disclosed method selects optimal switch architectures for specific applications. Embodiments support simultaneous, multicast transfers of data retrieved from a memory bank to a plurality of memory clients.

Computing device with circuit switched memory access

An SoC maintains the full flexibility of a general-purpose microprocessor while providing energy efficiency similar to an ASIC by implementing software-controlled virtual hardware architectures that enable the SoC to function as a virtual ASIC. The SoC comprises a plurality of 'Stella' Reconfigurable Multiprocessors (SRMs) supported by a Network-on-a-Chip that provides efficient data transfer during program execution. A hierarchy of programmable switches interconnects the programmable elements of each of the SRMs at different levels to form their virtual architectures. Arithmetic, data flow, and interconnect operations are also rendered programmable. An architecture index' points to a storage location where pre-determined hardware architectures are stored and extracted during program execution. The programmed architectures are able to mimic ASIC properties such as variable computation types, bit-resolutions, data flows, and amount and proportions of compute and data flow operations and sizes. Once established, each architecture remains in place as long as needed.

Energy efficient microprocessor with index selected hardware architecture

A method of synchronizing thread execution of a host and one or more coprocessors includes writing by the host of an event command and at least one coprocessor instruction to a FIFO and comparing of the event command with a current event register of the coprocessor until they match, whereupon the FIFO entries are popped and the instructions are forwarded to the coprocessor for execution. A plurality of entry groups can be written to the FIFO, each beginning with an event command. The instructions can direct the coprocessor to exchange data with shared memory and apply its thread to the received data. The processors and shared memory can be linked by a ring-type bus having a controller that performs the comparison, popping, and instruction forwarding. The coprocessor clears the current event register during thread execution, and then writes an event command to the register when processing is complete.

Method of synchronizing host and coprocessor operations via FIFO communication

A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, Time Fields are added to the instruction format for all programming units that specify the number of clock cycles for which only one fetched and decoded instruction will be executed.

Reconfigurable microprocessor hardware architecture

A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, a Time Field is added to the instruction format for all programming units that specifies the number of clock cycles for which only one instruction fetch and decode will be performed.

A multi-core processor includes a tree-like structure having a plurality of computing cores arranged in hierarchical levels, the cores all having the same logical architecture. Each core can include computing, interconnecting, and/or storage elements. The functionality of an individual element can be supplied by an entire core in a lower level. A method for programming the processor includes hierarchically decomposing an application into interconnected sub-functions, mapping the sub-functions onto groups of cores at appropriate levels of the processor, and interconnecting the mapped sub-functions so as to hierarchically compose the complete application. Sub-functions can be sequential, concurrent, and/or pipelined. Interconnections can be static or dynamically switchable under program control. Interconnect elements can also be used to implement flow control as needed in pipelined operations to maintain data coherency. The decomposing and mapping process can be iterated on sub-functions so as to optimize load balancing, software performance, and hardware efficiency.

Hierarchical multi-core processor and method of programming for efficient data processing

A dynamically reconfigurable network architecture includes a plurality of switching modules arranged in an ordered, multi-level, switched-tree configuration. A network is formed by selecting one switching module as the root and assigning it and all directly or indirectly subsidiary modules to the network. The operating mode of each switching module can be dynamically selected as either circuit-switched or packet-switched. The modules can be grouped into a single network or into a plurality of separate networks operating in parallel, including both circuit-switched and packet-switched networks. When a network is no longer needed, its operation can be halted and its resources released for reassignment to other networks. In embodiments, a selector controlled by allocation registers selects either a circuit-switching sequencer or a packet connection arbitration circuit to control the switching circuits. Switching modules can include crossbar switches. Circuit-switched connections can use TDM to share allocated physical resources.

Dynamically reconfigurable hybrid circuit-switched and packet-switched network architecture

A configurable adaptive variable length data packet transmission output scheduler for enabling substantially simultaneous transmission on a common transmission link, as of fiber optics, of differentiated services for various different traffic types, executing different QOS algorithms while co-existing in a converged network environment, with simultaneous preserving of the different service characteristics for real-time or high-priority traffic and providing differentiated bandwidth allocation while achieving maximal link utilization&#x2014;all through a fine and balanced control as to which type of traffic is transmitted on the link for a given duration, and how much of that traffic is transmitted on the link.

Method and apparatus for packet transmission with configurable adaptive output scheduling

In the routing of data traffic to a common destination egress queue from a plurality of customer subscribers each contracting for respective allocations of bandwidth of data flow, a technique and system for fairly sharing any underutilized excess bandwidth and for data dropping amongst over-subscribers, while guaranteeing each subscriber its contracted-for bandwidth, and further enabling billing over-subscribers for their share of received excess bandwidth&#x2014;all while maintaining the granularity of the contracted traffic flow.

Method and apparatus for fairly sharing excess bandwidth and packet dropping amongst subscribers of a data network

Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Instruction set design, control and communication in programmable microprocessor cores and the like

A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured by software for each specific application by communication through a switch fabric in a dynamic, parallel and flexible fashion to achieve a reconfigurable pipeline, wherein the length of the pipeline stages and the order of the stages varies from time to time and from application to application, admirably handling the explosion of varieties of diverse signal processing needs in single devices such as handsets, set-top boxes and the like with unprecedented performance, cost and power savings, and with full application flexibility.

Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing

The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions

Method of and apparatus for variable length data packet transmission with configurable adaptive output scheduling enabling transmission on the same transmission link(s) of differentiated services for various traffic types

A novel fault-tolerance technique for protecting against and correcting errors in packet data stream flow, preferably through not exclusively with closed ring sequential address generators and the like, through the use of pairs of independent but linked packet data flow paths enabling discarding of error data occurring in one path and substituting therefor corresponding correct data from the other path to enable continuation of the data stream flow without interruption and without error.

Method of and apparatus for correcting errors in data packet flow streams as in closed ring sequential address generators and the like without data flow stream interruption

Growing community of inventors

Concord, MA, United States of America

Xiaolin Wang