Globalfoundries U.S. Inc.

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Xiaoli Hu

Wei Zhao

Igor Arsovski

Qing Li

Xiaoxiao Li

Venkatesh P Gopinath

Shuangdi Zhao

Xueqiang Dai

Hao Pu

Bipul C Paul

George Maria Braceras

Thomas Melde

Chao Meng

Jieyao Liu

Xiaohua Cheng

Xi Cao

Yuzheng Jin

Nicki N Mika

Yuqing Sun

Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes. The structure further comprises a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes. The first top electrode is shared by the first plurality of resistive memory elements, and the second top electrode is shared by the second plurality of resistive memory elements.

Resistive memory element arrays with shared electrode strips

Embodiments of the disclosure provide a circuit structure and related method to compensate for sense amplifier leakage. A circuit structure according to the disclosure includes a reference voltage generator coupling a supply voltage and a reference line to a sense amplifier. A multiplexer within the reference voltage generator is coupled to the reference line. The multiplexer includes a plurality of transistors each having a gate terminal coupled to ground.

Circuit structure and related method to compensate for sense amplifier leakage

Structures herein include an array of non-volatile memory cells. The non-volatile memory cells include memory bit cells and at least one reference bit cell that is adjacent the memory bit cells. These structures also include at least one reference voltage regulator connected to the reference bit cell, and at least one sense amplifier connected to the memory bit cells and the reference voltage regulator.

Non-volatile memory device with reference voltage circuit including column(s) of reference bit cells adjacent columns of memory bit cells within a memory cell array

The present disclosure relates to integrated circuits, and more particularly, to a sense amplifier circuit for current sensing in a memory structure and methods of manufacture and operation. In particular, the present disclosure relates to a circuit including: a sensing circuit including a first set of transistors, at least one data cell circuit, and a reference cell circuit; a reference voltage holding circuit comprising a second set of transistors and a bitline capacitor; and a comparator differential circuit which receives a data sensing voltage signal from the sensing circuit and a reference voltage level from the reference voltage holding circuit and outputs an output signal.

Sense amplifier circuit for current sensing

A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.

Multi-port high performance memory

A structure includes a write driver circuit configured to drive both a true bitline side and a complement bitline side up to a power supply and down to ground such that one of the true bitline side and the complement bitline side is driven to ground and another of the true bitline side and the complement bitline side is driven to a high level at a same time and before a precharge below a level of the power supply of the one of the true bitline side and the complement bitline side.

Write scheme for a static random access memory (SRAM)

The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.

Sense-line muxing scheme

Devices include a primary transmission system, and first and second duplicate (dummy or non-transmitting) transmission systems. The primary transmission system includes a primary transmitter circuit receiving a data signal, a primary transmission line connected to the primary transmitter circuit, and a primary receiver circuit connected to the primary transmission line. The first duplicate transmission system is connected to the primary transmitter circuit, and supplies a transmission timing control signal to the primary transmitter circuit. The primary transmitter circuit stops transmitting (e.g., stops reducing the voltage of the primary transmission line) when the transmission timing control signal is received. The second duplicate transmission system is connected to the primary receiver circuit, and supplies an output timing control signal to the primary receiver circuit, and the primary receiver circuit outputs the data signal when the output timing control signal is received.

Transmission system having duplicate transmission systems for individualized precharge and output timing

The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on each unique entry as soon as a sense has been performed or completed.

Growing community of inventors

Shanghai, China

Xiaoli Hu