Intersil Americas Inc.

Xiaole Chen

Gustavo James Mehas

Sandeep Agarwal

Naveen Kumar Jain

Jayant Vivrekar

Atul Wokhlu

A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that establishes the over current protection trip point of the voltage regulator.

System and method for programming and controlling over current trip point limits in voltage regulators

A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.

Method for using digital PLL in a voltage regulator

Circuits, methods, and apparatus for adjusting an NCO output in order to provide a signal that is phase-locked to a reference signal. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to reduce the chance of metastability. During the first, the output of the NCO is phase shifted to the closest correct portion of a cycle of a clock signal. A second correction is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.

Phase error correction circuit for a high speed frequency synthesizer

Circuits, methods, and apparatus for reducing the phase error in an NCO clock output to reduce the clock jitter. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to obtain a substantially glitch-free, high-speed operation. During the first step, the output of the NCO is phase shifted to the closest quarter portion of a cycle of a clock signal. A second correction step is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.

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San Jose, CA, United States of America

Xiaole Chen