Intel Corporation

Xiaojun Weng

Marko Radosavljevic

Van H Le

Han Wui Then

Sansaptak W Dasgupta

Walid M Hafez

Paul B Fischer

Bernhard Sell

Rahul Ramaswamy

Nidhi Nidhi

Travis W LaJoie

Johann Christian Rode

Allen B Gardiner

Shu Zhou

Yu-Wen Huang

Abhishek Anil Sharma

Samuel Jack Beach

Cheng Tan

Hui-Min Chuang

Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

Dielectric sidewall features for tuning thin film transistor (TFT) parasitics

Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.

III-N transistors integrated with thin-film transistors having graded dopant concentrations and/or composite gate dielectrics

Growing community of inventors

Portland, OR, United States of America

Xiaojun Weng