Qualcomm Incorporated

Xiaoju Yu

Jonghae Kim

Changhan Hobie Yun

Niranjan Sunil Mudakatte

Mario Francisco Velez

Wei-Chuan Chen

Nosun Park

Paragkumar Ajaybhai Thadesar

Francesco Carrara

Xia Li

Chang-Ho Lee

Bin Yang

Matthew Michael Nowak

Edgar Schmidhammer

Christian Hoffmann

Kai Liu

Stefan Leopold Hatzl

Daniel F Garcia

Manuel Hofer

Mark A Kuhlman

John Jong-Hoon Lee

Supatta Niramarnkarn

Peter Bainschab

Ashish Alawani

Kinfegebriel Amera Mengistie

Jeongkeun Kim

Rodrigo Pacher Fernandes

A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.

Package comprising a solder resist layer configured as a seating plane for a device

Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

Thermal paths for glass substrates

A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.

Solenoid structure with conductive pillar technology

Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.

Inductors formed with through glass vias

A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.

Integration of through glass via (TGV) filter and acoustic filter

Apparatus implementing various structures to decrease the distance between two inductive elements for tuning an inductance with greater variability (a wider tuning range). One example integrated circuit (IC) package generally includes a laminate, a solder resist layer disposed on an upper surface of the laminate, and a semiconductor die disposed above the laminate and comprising a first inductor. At least a portion of a second inductor is disposed above a section of the solder resist layer, the first inductor at least partially overlaps the second inductor, and there is a gap between the first inductor and the second inductor.

Close proximity tunable inductive elements

An inductor-capacitor (LC) filter includes an inductor having an asymmetric shape including at least one turn. The LC filter also includes serial capacitors coupled to the inductor at only one end of a continuous portion of the inductor. The serial capacitors continues the shape of the inductor. The capacitors are outside of a footprint of the continuous portion of the inductor.

Inductor with metal-insulator-metal (MIM) capacitor

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San Diego, CA, United States of America

Xiaoju Yu