Texas Instruments Corporation

Xiaoju Wu

Henry Litzmann Edwards

Pinghai Hao

Jozef C Mitros

Amitava Chatterjee

Akram Ali Salman

Farzan Farbiz

Binghua Hu

James Robert Todd

Imran Khan

Tathagata Chatterjee

Robert M Higgins

Li Wang

Jonathan Philip Davis

Shariq Arshad

Stephanie Leanne Hilbun

Chin-yu Tsai

C Matthew Thompson

Sameer P Pendharker

Robert James Todd

Seetharaman Sridhar

Alexei Sadovnikov

Andrew Derek Strachan

Vladimir Frank Drobny

Sudheer Prasad

Shanjen Pan

John Kenneth Arch

Xinfen Chen

Qingfeng Wang

Fan-Chi Hou

Zafar Imam

Mohamed Kamel Mahmoud

Zhengyu Wang

Dhanoop Varghese

Fan Chi Hou

Yvonne Patton

Venugopal Balakrishna Menon

Rajesh Keloth

Larry B Anderson

A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

Shallow trench isolation processing with local oxidation of silicon

A semiconductor controlled rectifier (FIG.A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region () having a first conductivity type (N) and a first heavily doped region () having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region () having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region () having the first conductivity type is formed within the second lightly doped region. A buried layer () having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region () having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region () having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

ESD protection circuit with isolated SCR for negative voltage operation

The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

High reliability polysilicon components

Described examples include integrated circuits, drain extended transistors and fabrication methods in which a silicide block material or other protection layer is formed on a field oxide structure above a drift region to protect the field oxide structure from damage during deglaze processing. Further described examples include a shallow trench isolation (STI) structure that laterally surrounds an active region of a semiconductor substrate, where the STI structure is laterally spaced from the oxide structure, and is formed under gate contacts of the transistor.

Protection of drain extended transistor field oxide

Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

Drain extended transistor

A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.

Drain extended NMOS transistor

Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

Drain centered LDMOS transistor with integrated dummy patterns

A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.

A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

P-channel DEMOS device

An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.

Output driver with power down protection

In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.

Semiconductor device with extended electrically-safe operating area

Growing community of inventors

Irving, TX, United States of America

Xiaoju Wu