Chinese Academy of Sciences

Shanghai Zhaoxin Semiconductor Co., Ltd.

Xiaojing Li

Hao Zhang

Ming Liu

Changqing Xie

Dongmei Li

Shengfa Liang

Qing Luo

Yu Liu

Long Wang

Yi Bu Li

Wei Lin

Xin Chen

Lei Zhou

Miao Liu

Jiebin Niu

Jerming Lin

Shuang Zhan

Peiwen Zhang

Di Al

Hongzhang Yang

A method for designing a power network is provided and includes: initializing via widths and power-trace widths; determining whether utilization rates of first, second and third routing tracks are respectively equal to first, second and third values; when said utilization rate of said first routing tracks is not equal to said first value, adjusting said distance between first and second power traces until said utilization rate thereof is equal to said first value; when said utilization rate of said second routing tracks is not equal to said second value, adjusting said distance between third and fourth power traces until said utilization rate thereof is equal to said second value; and when said utilization rate of said third routing tracks is not equal to said third value, adjusting said distance between fifth and sixth power traces until said utilization rate thereof is equal to said third value.

Method for designing power network and power network

A method for predicting an operation parameter of an integrated circuit includes the following steps. A plurality of cells used by the integrated circuit are provided. A voltage-frequency sweep test is performed on each of cells through a test model to generate a plurality of parameters, wherein the parameters correspond to a voltage value. A lookup table is established according to the parameters. A timing signoff corresponding to the integrated circuit is obtained. A timing analysis is performed on a plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain a critical timing path, and the operation parameter of the integrated circuit is predicted according to the critical timing path.

Method and device for predicting operation parameter of integrated circuit

The present disclosure provides a method for cleaning a lanthanum gallium silicate wafer which comprises the following steps: at a step of 1, a cleaning solution constituted of phosphorous acid, hydrogen peroxide and deionized water is utilized to clean the lanthanum gallium silicate wafer with a megahertz sound wave; at a step of 2, the cleaned lanthanum gallium silicate wafer is rinsed and dried by spinning; at a step of 3, a cleaning solution constituted of ammonia, hydrogen peroxide and deionized water is utilized to clean the lanthanum gallium silicate wafer with the megahertz sound wave; at a step of 4, the cleaned lanthanum gallium silicate wafer is rinsed and dried by spinning; and at a step of 5, the rinsed and dried wafer is placed in an oven to be baked. The present invention shortens a period of acidic cleaning process and prolongs a period of alkaline cleaning and utilizes a more effective cleaning with megahertz sound wave to replace the conventional ultrasonic cleaning to solve the issue of cleaning the lanthanum gallium silicate wafer after a cutting process and to improve surface cleanliness of the lanthanum gallium silicate wafer to get a better cleaning effect.

Method for cleaning lanthanum gallium silicate wafer

A sampler adapted to a one-dimension slow-varying signal, including: a signal preprocessing unit configured to preprocess an input signal; a slope-controllable sawtooth wave signal generating unit configured to generate a slope-controllable sawtooth wave signal and perform zero-resetting; a signal comparing unit configured to compare the preprocessed input signal from the signal preprocessing unit with the sawtooth wave signal and to output a pulse signal to the generating unit and a signal outputting unit when the preprocessed input signal is equal to the sawtooth wave signal; a counting unit configured to count a number of clock signals while the sawtooth wave signal generating unit is generating the sawtooth wave signal and to transmit the counted number to the signal outputting unit; the signal outputting unit configured to, upon receipt of the pulse signal output from the signal comparing unit, output the number counted by the counting unit at the moment.

Random sampler adapted to one-dimension slow-varying signal

A method for collecting a signal with a frequency lower than a Nyquist frequency includes, by a data transmitting end, selecting a suitable transformation base matrix for an input signal, deriving a sparse representation of the signal using the transformation base matrix to determine a sparsity of the signal, calculating a number M of compressive sampling operations according to the sparsity, sampling the signal with fusing M channels, and integrating sampling values of each channel to obtain M measurement values. A reconstruction end reconstructs an original signal by solving optimization problems. Based on theory, compressive sampling can be performed on a sparse signal or a signal represented in a sparse manner with a frequency much lower than the Nyquist frequency, overcoming restrictions of the typical Nyquist sampling theorem. The method can be implemented simply and decrease pressure on data collection, storage, transmission and processing.

Method for collecting signal with sampling frequency lower than Nyquist frequency

The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of HPtClso as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt. The present invention is simple and practical and the sensitivity and reliability of the doped sensor on the gas of CO and Hare greatly improved.

Method for manufacturing ordered nanowire array of NiO doped with Pt in situ

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Beijing, China

Xiaojing Li