Ciena Corporation

Xiaojin Liu

Bashar Abdullah

Vahid M Naraghi

Sebastien Gareau

Kelly Donald Fromm

Daniel Lee

Daniel Claude Perras

Michel Desjardins

Systems, circuits, and methods for synchronizing devices in the time-domain are provided. A method, according to one implementation, includes determining a round-trip number based on a width of one cycle of a timestamping clock signal. The round-trip number is equal to a plurality of times that a clock signal is to be transmitted in a loop from a timing-leader component to a timing-follower component and back to the timing-leader component. The method also includes utilizing the timestamping clock signal to detect a cumulative time delay that results when the clock signal is transmitted in the loop a number of times equal to the round-trip number. The cumulative time delay is configured to enable synchronization of the timing-follower component with the timing-leader component.

Detecting time delay between circuits to achieve time synchronization

Systems and methods of storing phase history, and enhancing and restoring phase accuracy for a embedded Global Navigation Satellite System (GNSS) receiver include storing a phase history of the GNSS receiver output; determining an expected value of phase of the GNSS receiver output based on the phase history; and, responsive to a degradation of the GNSS receiver output, adjusting the GNSS receiver output utilizing the expected value of phase. The systems and method can further include, responsive to degradation being a loss of the GNSS receiver output, utilizing a holdover output from a physical frequency reference and with a phase adjusted based on the expected value of phase, and, responsive to the variation, utilizing the phase history to re-generate the GNSS receiver output for performance enhancement.

Phase clock performance improvement for a system embedded with GNSS receiver

A node can include a clock; and mapper circuitry configured to determine a timestamp from the clock, and transmit the timestamp to a second node in a Radio over Ethernet (RoE) frame with the timestamp in a control subtype and with an operational code (opcode) that designates the timestamp is in the frame. The node can also include a demapper circuit configured to receive a second timestamp from the second node in a second RoE frame, and provide the second timestamp to a Differential Clock Recovery (DCR) circuit for adjustment of the clock to a second clock at the second node.

Carrying a timestamp in radio over ethernet

Systems and methods of compensating for the delay asymmetry of coherent optical modems in a packet optical network include measuring fill levels of one or more queues each including an elastic First-In-First-Out (FIFO) circuit used in a transport mapping scheme, wherein the transport mapping scheme is one or more of client mapping to Optical Transport Unit (OTU) and OTU mapping to Flexible OTN (FlexO); and performing adjustments in a clock based in part on the measured fill levels, wherein the adjustments are configured to reduce a Time Error (TE) in the packet network based on delay asymmetry between two nodes.

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Ottawa, Canada

Xiaojin Liu