Changxin Memory Technologies, Inc.

Xiaojie Li

Daohuan Feng

Yi Tang

Mengmeng Yang

Jianfeng Xiao

Xiaoling Wang

Meng Huang

Pan Yuan

Dahan Qian

Hong Wang

A method includes: providing a substrate including a first region and a second region; a stacked structure being formed on the substrate, the stacked structure including a first semiconductor layers and a second semiconductor layers stacked alternately in sequence along a direction perpendicular to a plane where the substrate is located; etching the stacked structure, such that the first semiconductor layers and the second semiconductor layers located in the second region respectively form a first sub-part extending in a first direction and a third sub-part extending in the first direction; the first semiconductor layers and the second semiconductor layers remaining in the first region respectively constitute a second sub-part extending in a second direction and a fourth sub-part extending in the second direction; removing the third sub-part; and forming a first dielectric layer at least filling a gap between two adjacent ones of the first sub-parts.

Method for manufacturing semiconductor structure, semiconductor structure and three-dimensional structure

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base, and forming active pillars, a bit line, a word line, and memory structures. Forming the memory structures includes: providing an isolation layer between the word line and the memory structures, and forming a first conductive layer, a dielectric film, and a second conductive layer that are continuously and sequentially stacked on a side surface of the isolation layer and a surface of the active pillar; and etching to remove a part of the first conductive layer located on the side surface of the isolation layer, to expose a side surface of the dielectric film, and taking a remaining part of the first conductive layer as the first electrode plate.

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure. The semiconductor structure includes: a plurality of word lines extending along a first direction and arranged at intervals along a third direction; a plurality of semiconductor channels extending along a second direction and arranged at intervals along the third direction, wherein the word line surrounds the semiconductor channel along the third direction; a stepped structure including a plurality of steps, wherein the step is in contact with and connected to the word line, a height of a top surface of any one of the steps is different from a height of a top surface of another one of the steps along the third direction, the steps are arranged in an array along the first direction and the second direction; and a plurality of contact structures, wherein the contact structure is in contact with and connected to the step.

Semiconductor structure

A semiconductor structure manufacturing method includes: providing a substrate and forming a groove in the substrate; forming a barrier layer on a sidewall of the groove; epitaxially growing a channel material from a bottom of the groove to form an intermediate structure in the groove; and removing a portion of the intermediate structure and a portion of the substrate to form a fin structure.

Semiconductor structure manufacturing method and semiconductor structure

This invention relates to a semiconductor structure and a method for forming the semiconductor structure. The method for forming a semiconductor structure includes the following steps: forming a stacking layer on a top surface of a substrate, where the stacking layer includes a plurality of semiconductor layers arranged at intervals in a first direction, and the stacking layer includes a transistor region, a capacitor region, and a bit line region, where the semiconductor layers include semiconductor columns arranged at intervals in a third direction; forming, in the capacitor region, a capacitor extending in the second direction; forming a word line in the transistor region, where the word line extends in the third direction and continuously covers the semiconductor columns arranged at intervals in the third direction; and forming a bit line in the bit line region, where the bit line extends in the first direction.

Method for forming three-dimensional semiconductor structure and semiconductor structure made thereof

The semiconductor structure forming method includes: providing a base, where the base includes a substrate, a plurality of first semiconductor layers and second semiconductor layers; forming a first sidewall and a second sidewall, each including a support layer and an isolation layer formed on a side of the support layer; forming a plurality of recessed portions separated by the first sidewall, the second sidewall, and the second semiconductor layers, where the recessed portions extend in a horizontal direction and are stacked in a vertical direction; forming a first conductive layer and a filling layer in each recessed portion; removing isolation layers located on a side of the first sidewall that is away from the second sidewall and on a side of the second sidewall that is away from the first sidewall; and removing the first conductive layer located at a bottom of each recessed portion.

Semiconductor structure, method for forming semiconductor structure, and memory

A semiconductor structure comprises a substrate, wherein the substrate is provided with a stacked structure, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction, the stacked structure further comprising a plurality of horizontal signal lines arranged in the second direction, wherein each of the horizontal signal lines is in contact with one layer of the memory cells; and a plurality of leading wire posts arranged in the first direction, wherein the plurality of leading wire posts and the plurality of horizontal signal lines are arranged along a third direction, and the leading wire posts are connected to the horizontal signal lines.

Semiconductor structure and manufacturing method thereof, memory chip and electronic device

Embodiments relate to the field of semiconductors, and provide a semiconductor structure, including a substrate and connection lines. Structural cells arranged in an array are provided on the substrate, and include transistor groups arranged in a first direction, and the transistor groups include multi-layer transistors extending in a second direction. The first direction is perpendicular to the second direction, and both are parallel to a surface of the substrate. The structural cells further include bit lines extending in a third direction, the bit lines are electrically connected to the multi-layer transistors in the same transistor group, where the third direction is perpendicular to the surface of the substrate. The connection lines are connected to the bit lines in the structural cells in one-to-one correspondence, and one bit line in the structural cells arranged in the array is connected to the same connection line.

Semiconductor structure with a plurality of connection lines

Embodiments of the disclosure provide a semiconductor substrate, a method for forming same, and a layout structure. The method includes: providing a semiconductor structure including a first region and a second region arranged in sequence along a second direction, the second region including active structures arranged in an array along a first direction and a third direction, each of the active structure at least including a channel structure, the first direction, the second direction, and the third direction being perpendicular to each other, and the first direction and the second direction being parallel to a surface of the semiconductor substrate; forming a gate structure on a surface of the channel structure; and forming a word line structure extending in the first direction on the first region. The word line structure is connected with the gate structure located on the same layer.

Semiconductor structure, method for forming same, and layout structure

Embodiments relates to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a stacked layer on a top surface of a substrate, where the stacked layer includes a plurality of semiconductor layers spaced along a first direction, the stacked layer includes a transistor region, and a capacitor region and a bit line region; forming a capacitor extending along the second direction in the capacitor region; forming a word line in the transistor region, the word line extending along the first direction; and forming a bit line in the bit line region, the bit line extending along the third direction.

Semiconductor structure and formation method thereof

Embodiments of the present disclosure provide a semiconductor device, comprising a semiconductor layer, extending along the first direction; the semiconductor layer includes a capacitor area facing the capacitor structure, and the capacitor structure includes: a lower electrode layer, the capacitor dielectric layer and the upper electrode layer, sequentially surrounding the sidewalls of the capacitor area extending along the first direction, a part of the lower electrode layer surrounds the sidewalls of the capacitor region, and also surrounds the bottom of the upper electrode layer, the sidewalls extending along the first direction, and the capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer. The disclosed device improves the capacitance of the capacitor structure while improving the integration density of the semiconductor structure.

Semiconductor structure and a method of making the same

A semiconductor structure includes a substrate; at least one layer of memory structure formed on the substrate, in which each layer of memory structure comprises a bit line structure and a plurality of capacitor structures symmetrically distributed on both sides of the bit line structure, the plurality of capacitor structures and the bit line structure extend in a first direction parallel to the substrate surface; a plurality of word line structures formed in the at least one layer of memory structure, which pass through the at least one layer of memory structure and extend in a second direction perpendicular to the substrate surface.

Three-dimensional memory device with capacitors and vertical word-line

A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.

Memory and method for preparing memory

A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first and second regions; forming a first dielectric layer on the semiconductor substrate; forming a temporary layer on the first dielectric layer; performing a first heat treatment process on the first dielectric layer and the temporary layer; removing the temporary layer to expose the first dielectric layer; and performing a second heat treatment process on the first dielectric layer.

Method for manufacturing semiconductor device and semiconductor device

Provided are a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory. The method includes the following operations. An initial semiconductor structure is formed on a substrate. The initial semiconductor structure is etched to form an array area structure and a peripheral area structure including a peripheral area gate structure. An isolation wall surrounding the peripheral area gate structure is formed on the substrate where the peripheral area structure locates. A second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure. The second dielectric layer, the first dielectric layer and the isolation wall are etched to form the semiconductor structure with a flat surface.

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HEFEI, China

Xiaojie Li