Yangtze Memory Technologies Co., Ltd.

Xiaojiang Guo

Yu Wang

Zhuqin Duan

Bo Li

Daesik Song

Jin Yong Oh

Youxin He

Jialiang Deng

Zhichao Du

Ye Tian

ZhiChao Du

Siyuan Wang

Jong Hoon Kang

Hongtao Liu

Haibo Li

Yi Zhang

Chao Zhang

Yan Wang

Ke Jiang

Teng Chen

Masao Kuriyama

Chenhui Li

Jing Wei

Xiaodong Mei

Jinchi Han

Zhenjia Chen

In certain aspects, a method for programming a memory device includes caching first program data and preparing first program information, performing a first program operation using the first program data and the first program information, during the first program operation, caching a second program data in a first cache latch and preparing second program information, and after the first program operation is completed, performing a second program operation using the second program data and the second program information.

Memory device and method for performing cache program on memory device

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. A switch erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switch erase operation. The switch erase operation is different from the first erase operation on the memory array in the first storage mode.

Erase and program operations for memory devices having multiple storage modes

A memory device includes memory cells coupled to a same word line and bit lines, respectively, and a peripheral circuit coupled to the memory cells through the word and bit lines. Each memory cell is in one state. The peripheral circuit is configured to determine a first number of a first set of the memory cells and a second number of a second set of the memory cells in parallel. Threshold voltages of the first set of the memory cells are between a first voltage and a second voltage larger than the first voltage. Threshold voltages of the second set of the memory cells are between the second voltage and a third voltage larger than the second voltage. The peripheral circuit is also configured to determine a first read level corresponding to a first state based on the first number and the second number.

Memory device and operation method with optimized read level

A verify failbit count (VFC) circuit includes a counter including a plurality of counter stages coupled one after another and including one or more cache stages in a cache group and a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages. Each of the reception stages is configured to receive one of a plurality of verification bits generated by a verification operation of a memory device. The counter further includes one or more switches each coupled between two neighboring ones of the plurality of reception groups.

Digital verify failbit count (VFC) circuit

A memory device includes a memory array having memory cells, a page buffer coupled to the memory array through bit lines and including a latch, and a control logic coupled to the page buffer. The control logic is configured to perform a first read operation on the memory cells, and perform a second read operation on the memory cells by dividing the memory cells into a plurality of groups of memory cells, and performing a second read operation on the plurality of groups of memory cells based on a first set of develop times. Each of the first set of develop times is different. The control logic is also configured to perform a third read operation on the memory cells by performing a third read operation on the plurality of groups of memory cells based on a second set of develop times. Each of the second set of develop times is different. The control logic is further configured to determine a read develop time based on the third read operation.

System and method of performing a read operation

A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a programming voltage incremented with a first step size; verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size less than the first step size.

Methods for programming a memory device, memory devices, and memory systems

A method includes performing a programming operation on the memory cell using incremental step pulse programming. The programming operation includes applying one or more first voltage steps to the word line using a first step value to increase a threshold voltage of the memory cell toward a programming state. The programming operation also includes determining a quantity of memory cells that have a threshold voltage between first and second verification voltages. The second verification voltage is less than the first verification voltage and outside of a range of threshold voltages corresponding to the programming state. The programming operation also includes determining a step adjustment value based on the determining of the quantity. The programming operation also includes adjusting the first step value using the step adjustment value.

Memory device, programming method of memory device, and memory system

In certain aspects, a memory device includes a plurality of memory cells and a peripheral circuit coupled to the plurality of memory cells. The peripheral circuit includes a page buffer, which includes a page buffer circuit and control logic coupled to the page buffer circuit. The page buffer circuit includes a dynamic storage unit and a first non-dynamic storage unit. The control logic is configured to determine whether an information swapping process is performed between the dynamic storage unit and the first non-dynamic storage unit based on a type of an operation to be performed on the page buffer circuit and an information storage manner between the dynamic storage unit and the first non-dynamic storage unit. The control logic is further configured to perform the operation on the page buffer circuit based on the determining whether the information swapping process is performed.

Memory device, memory system, and operation method thereof

A method includes applying a first read voltage to a word line corresponding to a first word line address in a first read request instruction. The method also includes detecting an obtained second read request instruction. The method further includes when the second word line address included in the second read request instruction is the same as the first word line address, applying a second read voltage to the word line corresponding to the first word line address after the end of the application of the first read voltage.

Method for reading memory, a memory, a memory system, and electronic device

A circuit includes a voltage generator and a sensing device. The voltage generator includes a first output and a second output. The first output is configured to output a word line voltage, and the second output is configured to output a flag signal indicates a relationship between the word line voltage and a reference signal. The sensing device includes a first input and a third output. The first input is coupled to the second output of the voltage generator, and the third output of the sensing device is configured to output a value corresponding to capacitance change of word line capacitance loading based on the flag signal.

Memory device and operation thereof

The present disclosure provides a memory device that includes a memory array and a page buffer. The memory array includes a plurality of memory cells coupled to a bit line of the memory array. The page buffer is coupled to the plurality of memory cells via the bit line to sense stored data in the memory cells. The page buffer includes first, second, and third transistors coupled to the bit line, first and second nodes, a capacitance structure coupled to the first node, and a latch circuit coupled to the bit line via the first transistor. First terminals of the first, second, and third transistors are coupled to the first node. A second terminal of the second transistor is coupled to the second node. The third transistor amplifies a read margin voltage at the second node. The page buffer shortens a time of a read operation or verify operation.

Memory device including page buffer, memory system including page buffer, and operating method thereof

Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to determine that a block of the blocks is an open block based on an open block information, and in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Open block-based read offset compensation in read operation of memory device

Implementations provide a memory, a method for operating a memory, and a memory system. The discloses method can comprises: applying a multi-plane programming scheme to simultaneously perform programming operations on at least two memory planes of the memory device; and in response to determining that an exceptional memory plane of the at least two memory planes has a programming failure, switching to a single-plane programming scheme to sequentially perform programming operations on the at least two memory planes.

Memory device, method for operating memory device, memory system

A memory device, a method for programming the memory device, a program verification method, and a memory system are provided. In the program verification method, an iverification result of an iprogram verification operation is obtained, where programming states verified by the iprogram verification operation range from an nstate to an (n+k)state, i and n are positive integers, k is a natural number, and the (n+k)state is less than or equal to a highest programming state of the memory device; a range of programming states to be verified by an (i+1)program verification operation is determined according to a verification sub-result for the nstate and a verification sub-result for the (n+k)state in the iverification result; and the (i+1)program verification operation is executed according to the determined range of the programming states to be verified by the (i+)program verification operation.

Memory device, method for programming memory device, program verification method and memory system

A method for reading a memory device is provided. The memory device includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and each of the multi-bit memory cells is configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages. The method includes: defining at least one read offset for each of the multi-level preset read voltages respectively, selecting at least one of the multi-level preset read voltages as at least one sampling voltage, reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell, and setting at least one offset flag, each representing a size of a respective one of at least one read offset, according to a sampling reading value of each of the at least one sampling voltage.

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Wuhan, China

Xiaojiang Guo