Micron Technology Incorporated

Intel Corporation

Xiaojiang Guo

Michele Piccardi

Qiang Tang

Kalyan C Kavalipurapu

Manan Tripathi

Guanglei An

Ramin Ghodsi

Shigekazu Yamada

Yogesh Luthra

Kim-Fung Chan

Jung Sheng Hoei

Eric N Lee

Chang Wan Ha

Dean K Nobunaga

Ali Feiz Zarrin Ghalam

Jonathan Scott Parry

Feng Q Pan

June Lee

Liang Yu

Naveen Kaushik

Weihua Shi

Shuai Xu

Ruo-Gu Huang

Kalyan Chakravarthy C Kavalipurapu

Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

Capacitor in a three-dimensional memory structure

A sample and hold scheme for temperature measurements for non-volatile memory can enable significant reduction in temperature readout latency. In one example thermometer circuits are enabled at a refresh rate to cause the temperature to be sensed and latched at regular intervals. By performing the temperature readings in the background at a refresh rate instead of on-demand, the temperature is available to service commands with almost no latency.

Thermometer sample and hold design for non-volatile memory

Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

Power management

Methods might include determining whether a particular die of a plurality of dies is expected to initiate a next phase of an operation, setting an expected peak current magnitude of the particular die to the present expected peak current magnitude in response to the expected peak current magnitude of the next phase being less than a present expected peak current magnitude, and setting the expected peak current magnitude of the particular die to the expected peak current magnitude of the next phase in response to the expected peak current magnitude of the next phase being greater than the present expected peak current magnitude if a sum of the expected peak current magnitude of the next phase, and expected peak current magnitudes for each die of the plurality of dies other than the particular die, is less than a particular value. Apparatus might be configured to perform similar methods.

A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

NAND flash array defect real time detection

Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.

Standby biasing techniques to reduce read disturbs

Apparatus, systems, and methods are disclosed, including a high-voltage charge pump including multiple pump stages connected in series to provide a high-voltage output, a common discharge circuit, and multiple high-voltage devices coupled between the outputs of each of the multiple pump stages and the common discharge circuit. Each of the multiple pump stages include a low-voltage switching device. The common discharge circuit is coupled to each of the multiple pump stages and is configured to discharge the multiple pump stages when the multiple pump stages are disabled. The multiple high-voltage devices include a respective high-voltage device coupled between an output of each of the multiple pump stages and the common discharge circuit.

Stage protection in multi-stage charge pumps

Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line.

Low-voltage bias generator based on high-voltage supply

Methods of operating a memory, and memories having a controller configured to cause the memory to perform such methods, include applying a plurality of first voltage levels to an access line, applying a plurality of second voltage levels to a control gate of a string driver connected to the access line for a first portion of the plurality of first voltage levels with each second voltage level of the plurality of second voltage levels being greater than a respective first voltage level by a first voltage differential, and applying a plurality of third voltage levels to the control gate of the string driver for a second portion of the plurality of first voltage levels with each third voltage level of the plurality of third voltage levels being greater than a respective first voltage level by a second voltage differential less than the first voltage differential.

Adjusting voltage levels applied to a control gate of a string driver in a memory

An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable.

Peak current management in a memory array

Methods of operating a die might include determining an expected peak current magnitude of the die for a period of time, and outputting the expected peak current magnitude from the die prior to completion of the period of time. Apparatus might be configured to perform similar methods.

A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to the program voltage target; a sensor circuit that compares a duty cycle of the control signal to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

Integrated circuit devices might include a controller configured to cause the integrated circuit device to apply a first voltage level to a first conductor while applying a second voltage level to a second conductor, apply a third voltage level to the first conductor while applying a fourth voltage level to the second conductor, and apply a fifth voltage level to the first conductor while applying the second voltage level to the second conductor. The second voltage level might correspond to a target voltage level for the second conductor. A difference between the third voltage level and the first voltage level might have a polarity opposite the polarity of a difference between the fourth voltage level and the second voltage level, and the same polarity of a difference between the fifth voltage level and the first voltage level. The fifth voltage level might correspond to a target voltage level for the first conductor.

Integrated circuit devices for driving conductors to target voltage levels

A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system is electrically coupled to a corresponding plane. The controller is configured to turn on and warm up each voltage generation system of the plurality of voltage generation systems in response to a first command to access any plane of the plurality of planes and turn off and slowly discharge each voltage generation system of the plurality of voltage generation systems into an idle state in response to no commands being processed. In response to receiving a subsequent command to access any plane of the plurality of planes prior to the voltage generation systems reaching the idle state, a warm up period of the plurality of voltage generation systems is reduced.

Growing community of inventors

San Jose, CA, United States of America

Xiaojiang Guo