Western Digital Technologies, Inc.

Nio Technology (anhui) Co., Ltd.

Xiaohua Liu

Liang Li

Qianqian Yu

Ming Cheng

Hongli Wang

David Joaquin Reed

Wenhui Shi

Weihao Wang

Yuxuan Liu

The invention relates to the technical field of vehicle charging, and particularly provides a vehicle charging port mounting assembly and a vehicle. The invention aims to solve the problem that existing charging port components have a poor design of mounting structure and thus cannot well meet the usage requirements. To this end, the vehicle charging port mounting assembly of the invention comprises a body side outer panel, a charging port component, a charging port mounting component, a rear wheel cover outer panel and a rear wheel cover outer panel reinforcing plate, wherein the charging port mounting component comprises a mounting bracket and an accommodation support member which is provided with an accommodation chamber, the mounting bracket being disposed in the accommodation chamber and fixedly connected to the accommodation support member, and the accommodation support member being disposed between the body side outer panel and the rear wheel cover outer panel. The charging port component is fixed by both the mounting bracket and the accommodation support member, thereby effectively improving the durability and NVH features of this region. The design requirement of dry-wet separation can also be effectively achieved by means of the accommodation support member, and the local strength of this region can be increased by means of the rear wheel cover outer panel reinforcing plate, thereby effectively meeting multiple requirements.

Vehicle charging port mounting assembly and vehicle

Apparatuses and techniques for detecting short circuits in a memory device, and in particular, word line-to-channel short circuits and short circuits between bit line contacts at the top of NAND strings. A short circuit detection operation includes a channel pre-clean phase which discharges a channel of a non-short circuited NAND string while boosting a bit line of a short circuited NAND string, followed by a bit line pre-charge phase which boosts a bit line of the non-short circuited NAND string, followed by a bit line discharge phase which discharges the bit line of the non-short circuited NAND string, followed by a sensing phase which identifies the short circuited NAND strings as being in a programmed or non-conductive state.

All bit line sensing for determining word line-to-memory hole short circuit

Apparatuses and techniques are described for performing an operation which irreversibly prevents access to a set of memory cells. The operation provides a strong erase bias for select gate transistors of NAND strings. The erase bias induces a phenomenon in the select gate transistors which permanently increases their threshold voltages. This prevents access to the memory cells such as for program or read operations. The operation can involve one or more erase-verify iterations. In each erase-verify iteration, an erase bias is applied to the select gate transistors such as by charging up the channels of the NAND strings and holding a control gate voltage of the select gate transistors at a relatively low level, thereby causing a relatively high channel-to-control gate voltage.

Instant and permanent self-destruction method in 3D NAND for data security purpose

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Shanghai, China

Xiaohua Liu