Qualcomm Incorporated

Xiaohua Kong

Zhi Zhu

Nam Dang

Miao Li

Cheng Zhong

Li Hsiang Sun

Jie Xu

Lew G Chua-Eoan

Madjid Hafizi

Tirdad Sowlati

Jingcheng Zhuang

Hung Quoc Vuong

Swarna Navubothu

Nir Gerber

Deqiang Song

Dong Ren

Vannam Dang

Glenn Murphy

Christian Josef Wiesner

Sei Seung Yoon

Matthew Levi Severson

Zhiqin Chen

Esin Terzioglu

Mikhail Popovich

Boris Andreev

Bupesh Pandita

Kenneth Arcudia

Mohamed Waleed Allam

Zhuo Gao

Ohjoon Kwon

William Knox Ladd

Wei Wang

Yan Hu

Jose Gilberto Corleto Mena

Behnam Amelifard

Amirali Shayan

Charlie Matar

Christopher Phan

Mauricio Calle

IK-Joon Chang

Li Sun

Swarna L Navubothu

Nam V Dang

Hung Q Vuong

Swarna Latha Navubothu

A pre-driver circuit generates a driver bias signal based on a swing command, a driver impedance characteristic, and an input signal. A driver receives the driver bias signal and generates, in response, a driver signal having a swing and having an output impedance corresponding to the bias signal. Optionally, the driver receives power from a switchable one of multiple supply rails, according to the swing. Optionally, the driver has voltage controlled resistor elements and the driver bias signal is generated based on the swing command and a replica of the driver voltage controlled resistor elements.

Multi-standard, automatic impedance controlled driver with supply regulation

An apparatus and methods are disclosed for a bidirectional front-end circuit included within a system on chip (SoC). The bidirectional front-end circuit includes a differential bidirectional terminal for receiving and transmitting signals. The bidirectional front-end circuit is configured to provide a first communication path between a first controller and a connector through the differential bidirectional terminal when operating in a first mode. And, the bidirectional front-end circuit is reconfigured to provide a second communication path between a second controller and the connector through the differential bidirectional terminal when operating in a second mode.

Apparatus and methods for providing a reconfigurable bidirectional front-end interface

An electronic device includes a receiver sense circuit configured to generate a detection signal responsive to detecting a connection to a sink device via a connector. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to enable a direct current (DC) voltage source based on the detection signal received from the receiver sense circuit.

Power saving during a connection detection

A plurality of drivers for driving corresponding differential data output signals are arranged in series such that a first current discharged by a first one of the drivers is recycled through remaining ones of the drivers.

Voltage mode driver with charge recycling

An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.

Controller-PHY connection using intra-chip SerDes

An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.

Apparatus and method for in situ analog signal diagnostic and debugging with calibrated analog-to-digital converter

In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal.

Switch capacitor decision feedback equalizer with internal charge summation

An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.

Split chip solution for die-to-die serdes

Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.

Unified front-end receiver interface for accommodating incoming signals via AC-coupling or DC-coupling

A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.

Linearity of phase interpolators by combining current coding and size coding

A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclically samples a data signal to form sets of samples according to the in-phase, quadrature, and auxiliary clocks, each set comprising an in-phase sample, a quadrature sample, and an auxiliary sample. A CDR logic circuit processes the samples to form a timing word for each set.

Multi-mode phase-frequency detector for clock and data recovery

In a particular embodiment, an electronic device includes a direct current (DC) voltage source coupled to a DC interface. The electronic device includes a receiver sense circuit configured to detect a connection of the electronic device to a sink device via a connector without consuming power from the DC voltage source. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to receive a detection signal from the receiver sense circuit, selectively control a switch to enable and disable the DC voltage source based on the detection signal, detect an HPD signal at the HPD interface after enabling the DC voltage source, and disable the receiver sense circuit in response to detecting the HPD signal.

A clock generator is provided that is immune to skew between bits in digital words generated by a multi-phase receiver.

Clock pulse generator for multi-phase signaling

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San Diego, CA, United States of America

Xiaohua Kong