Broadcom Corporation

Marvell International Limited

Xiaogang Zhu

Jonathan Fuchuen Lee

Ian A Swarbrick

Andrew Hwang

Yan Fan

A system on a chip includes a network, an interface and a bridge module. The network includes one or more devices. The network is configured to operate in a first domain. Communication in the first domain is based on a first set of read and write ordering rules. An interface is connected between the network and a second chip. Communication between the interface and the second chip is in a second domain. Communication in the second domain is based on a second set of read and write ordering rules. The second set of read and write ordering rules are different than the first set of read and write ordering rules. The bridge module is configured to map communication transactions between the first domain and the second domain.

Bi-domain bridge enhanced systems and communication methods

Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (&#xbc;) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.

Method and system for direct access memory testing of an integrated circuit

Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.

Automatically detecting types of external data flash devices

Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Method and system for hardware implementation of resetting an external two-wired EEPROM

Automatically detecting types of external FLASH devices is provided, and may comprise communicating one or more read memory device ID commands corresponding to at least one supported memory device to at least one memory device. Data received in response to this communication may be utilized to determine whether the received data identifies the memory device as one of the plurality of supported memory devices. The supported memory devices may be serial FLASH memory devices. Each read memory device ID command may be manufacturer specific, or may be specific to a group of the supported memory devices. The communicating of read memory device ID commands and determining whether the memory device is a supported memory device may be repeated if the memory device is not identified as one of the supported memory devices. There may be a limit to the number of times this is repeated.

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Fremont, CA, United States of America

Xiaogang Zhu