Applied Materials, Inc.

Sandisk Technologies Inc.

Xiaofeng Zhang

She-Hwa Yen

Steve Choi

Steve Fang

Gyusung Park

Albert I-Ming Chang

Naresh Battula

A method and circuit for performing vector operations may include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the operation to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector operation.

Adaptive settling time control for binary-weighted charge redistribution circuits

A method and circuit for performing multi-layer vector-matrix multiplication operations may include, at a first multiplier-accumulator (MAC) layer, converting a digital input vector using one-bit digital to analog converters (DACs); sequentially performing vector-matrix multiplication operations for the analog DAC signals; and sequentially performing an analog-to-digital (ADC) operation on outputs of the vector-matrix multiplication operations to generate binary partial output vectors. At a second MAC layer, the method and circuit may sequentially receive the binary partial output vectors from the first MAC layer at multi-bit DACs; and sequentially perform vector-matrix multiplication operations to generate a summed binary output for the second MAC layer.

Throughput and precision-programmable multiplier-accumulator architecture

A method for performing vector-matrix multiplication may include converting a digital input vector comprising a plurality of binary-encoded values into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs); sequentially performing, using an analog vector matrix multiplier and based on bit-order, vector-matrix multiplication operations using a weighting matrix for the plurality of analog signals to generate analog outputs of the analog vector matrix multiplier; sequentially performing an analog-to-digital (ADC) operation on the analog outputs of the analog vector matrix multiplier to generate binary partial output vectors; and combining the binary partial output vectors to generate a result of the vector-matrix multiplication.

Scalable, multi-precision, self-calibrated multiplier-accumulator architecture

A method and circuit for performing vector-matrix multiplication may include converting an input vector of binary-encoded values into analog signals using one-bit DACs, and sequentially performing a vector-matrix multiplication operation for each bit-order. The method may also include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the multiplier to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector-matrix multiplication.

A voltage regulator circuit is presented that can generate a stable and well-regulated output level to supply loads that have large dynamic current and capacitive variation. A compensation circuit is added to introduce a zero that tracks the voltage regulator's non-dominant pole. The compensation circuit includes a compensation transistor, whose gate is connected to receive the same voltage as the regulator's load driving pass transistor, and a series combination of a capacitance and a tracking resistance connected in series between the compensation transistor's gate and a supply level, where the value of the tracking resistance depends on the current supplied to the load. The tracking resistance can be implemented as a diode connected NMOS through which the compensation transistor is connected to the low supply level, or a diode connected PMOS whose current tracks that of the compensation transistor through a current mirror.

Non-dominant pole tracking compensation for large dynamic current and capacitive load reference generator

Apparatuses and techniques are described for calibrating a negative voltage source. A ground voltage is applied to a multi-stage amplifier from the negative voltage source while an offset voltage measurement (OVM) is made at the output of the multi-stage amplifier. The OVM is recorded and subsequently used by a calibration circuit when the negative voltage source applies a range of negative voltages to the input of the multiple stage amplifier. The calibration circuit subtracts the OVM from measurements obtained at the output of the multi-stage amplifier to obtain corrected measurements, and uses the corrected measurements to calibrate the negative voltage source, e.g., by adjusting a relationship between digital values input to the negative voltage source and the output voltages.

Accurate self-calibrated negative to positive voltage conversion circuit and method

Detecting a word line leakage in a non-volatile memory array. Various methods include: in a first step, enabling a M-bit 'coarse' digital-to-analog converter (DAC) logic of an N-bit analog-to-digital converter (ADC) to, according to a clock signal of the coarse DAC, compare a reference voltage and a biased input voltage of a load current of the memory array, wherein the reference voltage is dependent upon the voltage level at which the input voltage becomes non-linear, and, in a second step, if the input voltage is greater than or equal to the reference voltage, enabling a P-bit 'fine' ramp digital-to-analog converter (DAC) logic of the ADC to enable drawing a second current from the load current to ramp down the input voltage and to begin a counter and conduct leakage detection with the ADC when the input voltage is in the range between a first voltage and a second voltage.

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San Jose, CA, United States of America

Xiaofeng Zhang