Changxin Memory Technologies, Inc.

Xiaofeng Xu

Guangteng Long

Yang Wang

Peng Wang

Junwei Lian

A memory test method, a memory test apparatus, a device and a storage medium are provided. The memory test method includes: obtaining a central processing unit (CPU) accessible space of a memory to-be-tested; obtaining a graphics processing unit (GPU) accessible space of the memory to-be-tested; and driving a CPU to run a test program based on the accessible space of the CPU, to access the memory to-be-tested through a bus of memory to-be-tested, when the CPU runs the test program, the CPU controls a GPU to access the memory to-be-tested based on the accessible space of the GPU through the bus of memory to-be-tested.

Memory test method, memory test apparatus, device and storage medium

A semiconductor memory training method includes: selecting two adjacent reference voltages from a plurality of reference voltages as a first reference voltage and a second reference voltage; obtaining a first minimum margin value for the plurality of target signal lines under the first reference voltage; obtaining a second minimum margin value for the plurality of target signal lines under the second reference voltage, according to a minimum margin value for each target signal line under the second reference voltage; determining a target interval for an expected margin value according to the first minimum margin value and the second minimum margin value, the expected margin value being the maximum one among the minimum margin values for the plurality of target signal lines under the plurality of reference voltages; and searching for the expected margin value in the target interval.

Semiconductor memory training methods and related devices

The present disclosure provides a memory test method. The method includes: determining a refresh cycle T, a designed attack resistance frequency F, and a single row read time t of a target repository; determining an attack row quantity N based on the refresh cycle T, the designed attack resistance frequency F, and the single row read time t; determining a group of target attack rows in the target repository based on a value of the attack row quantity N, where the group of target attack rows include N target attack rows, and at least two of the N target attack rows are spaced apart by one row; detecting, after reading the N target attack rows for X consecutive times, whether data exception occurs in all adjacent rows of the target attack rows, to complete one attack test.

Memory test method

The present application relates to a semiconductor memory training method and related devices, belonging to the technical field of semiconductors. The method comprises: obtaining a stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage; setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage; obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; and using the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold.

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Hefei, China

Xiaofeng Xu