No. 24 Research Institute of China Electronics Technology Group Corporation

Chongqing Gigachip Technology Co. Ltd.

No. 24 Research Institute of China Electronic Technology Corporation

No. 24th Research Institute of China Electronics Technology Group Corp

Xiaofeng Shen

Dongbing Fu

Liang Li

Mingyuan Xu

Guangbing Chen

Xi Chen

Xingfa Huang

Jian'an Wang

Ting Li

Yuxin Wang

Ruzhang Li

Gangyi Hu

Jianan Wang

Jie Pu

Youhua Wang

Yong Zhang

Daiguo Xu

Tao Liu

Yabo Ni

Zhengping Zhang

Can Zhu

Lu Liu

Xueliang Xu

Jun Liu

Hongrui Yang

Shuiqin Yao

Xianjie Wan

Ruitao Zhang

Shutao Zhou

Kaiquan He

Jiahao Peng

Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight. Even if the manufacturing process or working environment of the current chip changes, perturbation weight can be dynamically adjusted, to ideally eliminate perturbation signal in digital signal.

Circuits, chips, systems and methods for eliminating random perturbation

A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

Clock drive circuit

The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.

One-time programmable capacitive fuse bit and a memory

The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M), a second MOS transistor (M) and a capacitor (C); a drain of the first MOS transistor (M) is connected to a negative terminal (CLK&#x2212;) of a differential clock, a gate of the first MOS transistor (M) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M) is connected to a drain of the second MOS transistor (M); a gate of the second MOS transistor (M) is connected to the negative terminal (CLK&#x2212;) of the differential clock, and a source of the second MOS transistor (M) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.

Differential clock cross point detection circuit and detection method

The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Circuit for generating multi-phase clock having random disturbance added thereto

The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.

High-speed regenerative comparator circuit

A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.

Duty cycle adjustment apparatus

The present invention provides a device and method for correcting error estimation of an analog-to-digital converter. The method comprises: according to a preset initial value of a correction parameter, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to the initial value of a correction parameter, correcting a gain error between channels, generating a general correction signal, buffering the general correction signal and triggering a counting cell to start counting, and meanwhile calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting up to a preset value, setting enable ends of a low-pass filter accumulating cell and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching the error estimation result, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and gain correction parameter, and resetting to carry out cyclic estimation correction. According to the present invention, in the case where a few effective sample points are used, the estimation accuracy is improved and the convergence rate of the estimation correction is increased.

Device and method for correcting error estimation of analog-to-digital converter

A pipeline A/D converter and its single redundancy bit digital correction are provided. The single redundancy bit digital correction includes the following steps: substages except for the last one quantizes input voltage, calculates the residual voltage, which is amplified and shifted to the middle part of the reference voltage range, and outputs to the following substage until the last one, which only quantizes the input voltage; the code and offset code of each substage corresponding to the quantized thermometer code are calculated; the offset codes of all stages are added by weight to get total offset code; and codes of all substages are added by weight, to which the total offset code is added. The comparator offset error is corrected to obtain an output code which identifies the negative or positive overflow of input signals. The A/D converter adopting the above digital correction is provided.

Pipelined analog-to-digital converter and its single redundancy bit digital correction technique

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Chongqing, China

Xiaofeng Shen