Jiangnan University

University of Virginia Patent Foundation

Xiaofeng Gu

Gary J Shiflet

S Joseph Poon

Zhiguo Yu

Hailian Liang

Qiang Xu

Hongbing Pan

Sheng Ding

Yanhang Liu

Haiyan Nan

Daqing Li

Feng Shao

Shaoqing Xiao

Huyun Liu

Hai Zhou

Xiaoyu Zhong

Disclosed are an offset calibration method and circuit applied to a comparator array. The offset calibration circuit includes a global calibration voltage generation module, integrators, comparators, a global logic control circuit, and local logic control circuits; an entire comparator array shares the single global calibration voltage generation module, and each of the comparators only needs to introduce an integrator circuit, such that a large calibration range and a small calibration step are achieved, a long calibration cycle and a large circuit area are required, and the requirements for a low area are satisfied. The offset calibration method provided by the present disclosure is similar to a binary search algorithm, which is adopted to search for the offset voltage, the calibration step of can be realized by only N cycles, and short calibration time is thus realized.

Offset calibration method and circuit applied to comparator array

The disclosure relates to a method for regulating photocurrent of IGZO based on a two-dimensional black phosphorus material, and belongs to the field of semiconductor devices. The disclosure provides a method for preparing an IGZO-black phosphorus heterostructure by dry transfer technology, and by changing the contact mode between IGZO and black phosphorus, photocurrent response of the IGZO to different laser light wavelengths can be regulated. In the method, both a channel and electrodes of the IGZO are magnetron sputtered by means of masks, and the method has good repeatability and can realize preparation of large-area multi-devices. A black phosphorus sample is prepared by a mechanical exfoliation method, and has controllable thickness and size. A heterojunction is prepared by dry transfer technology, and the technology is easy to operate and highly controllable. The disclosure is beneficial to promote development of IGZO thin films in the micro-nano field and the semiconductor industry.

Method for regulating photocurrent of IGZO based on two-dimensional black phosphorus material

The disclosure discloses a temperature compensation circuit and method for a neural network computing-in-memory array. Reference arrays sparsely inserted in the computing-in-memory array are adopted to provide a reference voltage for ADCs, so that an input voltage and a reference voltage of the ADCs have a same temperature coefficient. Finally, after analog-to-digital conversion by the ADC, the digital output of the ADC is not affected by the external temperature, thereby ensuring the operational precision of the neural network. According to the temperature compensation circuit of the disclosure, the reference arrays have the same structure as the computing-in-memory array. The insertion density of the reference arrays is related to the temperature field where the computing-in-memory arrays are located. One reference array may provide the reference voltage of the ADC for a plurality of computing-in-memory arrays, thereby minimizing the increase of area and power consumption caused by inserting the reference arrays.

Temperature compensation circuit and method for neural network computing-in-memory array

An ESD protection device for bidirectional diode string triggering SCR structure belongs to the field of electro-static discharge of an integrated circuit. A deep N well is arranged on a P substrate, and a first P well, a first N well, a second P well and a second N well are successively arranged from left to right on a surface region of the deep N well. In a second N well region, a mask preparing plate is used to insert the P wells at intervals. The circumference of each P well is isolated by the N well. Each P well is respectively provided with a pair of P+ implantation region and N+ implantation region. The metal wire is connected with the implantation region, and a positive electrode and a negative electrode are led out from the metal wire for forward conduction and reverse conduction.

ESD protection device with bidirectional diode string-triggering SCR structure

The present invention relates to novel non-ferromagnetic amorphous steel alloys represented by the general formula: Fe&#x2014;Mn-(Q)-B-M, wherein Q represents one or more elements selected from the group consisting of Sc, Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, and M represents one or more elements selected from the group consisting of Cr, Co, Mo, C and Si. Typically the atomic percentage of the Q constituent is 10 or less. An aspect is to utilize these amorphous steels as coatings, rather than strictly bulk structural applications. In this fashion any structural metal alloy can be coated by various technologies by these alloys for protection from the environment. The resultant structures can utilize surface and bulk properties of the amorphous alloy.

Non-ferromagnetic amorphous steel alloys containing large-atom metals

The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD protection for high voltage IC. Wherein said the device comprises a P substrate, a P well, a N well, a first field oxide isolation region, a first P+ injection region, a second field oxide isolation region, a first N+ injection region, a first fin polysilicon gate, a second N+ injection region, a second fin polysilicon gate, a third N+ injection region, a third fin polysilicon gate, a polysilicon gate, a fourth fin polysilicon gate, a second P+ injection region, a fifth fin polysilicon gate, a third P+ injection region, a sixth fin polysilicon gate, a fourth P+ injection region, a third oxygen isolation region, a fourth N+ injection region and a fourth field oxygen isolation region. Under the influence of ESD pulse, the ESD discharge current path with LDMOS-SCR structure and the RC coupling current path with embedded PMOS interdigital structure in the drain terminal and embedded NMOS interdigital structure in the source terminal are formed, in order to enhance the ESD robustness of the device and improve the voltage clamp capability.

Embedded high voltage LDMOS-SCR device with a strong voltage clamp and ESD robustness

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Xiaofeng Gu