Huazhong University of Science and Technology

Zhejiang Lab

Xiaofei Liao

Hai Jin

Long Zheng

Haikun Liu

Yu Zhang

Jin Zhao

Zhiyuan Shao

Qinggang Wang

Fan Zhang

Yu Huang

Xiang Hui Zhao

Yicheng Chen

Kai Chen

Dong Liang

Qingxiang Chen

Pengcheng Yao

Zhiwei Li

Xi Ge

Yuanyuan Ye

Beibei Si

Chengbo Yang

Dang Yang

Zhaozeng An

Ao Hu

Sitong Lu

Shijun Li

Hui Yu

Yujie Chen

Xinyu Jiang

Rentong Guo

Yun Yang

The present invention relates to a post-exascale graph computing method, and corresponding system, storage medium and electronic device. The invention solves the problems of low computing performance, poor scalability and high communication overhead in the large-scale distributed environment, and improves the performance of the supercomputer when supporting large-scale graph computing.

Post-exascale graph computing method, system, storage medium and electronic device thereof

A cache-designing method using cache lines to record cache-miss information is provided, wherein cache lines and cache-miss information are stored in a common storage space by means of shared storage. Tags of cache lines, as well as cache lines and cache-miss information, are stored separately in different static random-access memories, wherein multiple independent memories are used for tags, while a single memory is for cache lines and cache-miss information. A request-processing pipeline and a response-processing pipeline are constructed to be parallelable and used respectively for processing memory-access requests and for processing memory-response data. As compared to existing non-blocking cache designs that support plenty of miss status holding registers, the present disclosure allows storage sharing between cache data and cache-miss information, and leverages dual-port feature of static random-access memories in FPGA, so as to design separate pipelines to achieve memory access respectively for memory-access request processing and for memory-response data processing.

Cache-designing method where cache data and cache-miss information share the same storage space

The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermediate results. In view of the shortcomings of task-centric hardware accelerators, the present invention can prevent any possible data conflict during parallel execution of multiple processing units.

Hardware accelerator for hypergraph processing and operating method thereof

The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus has several searching and caching modules and several modifying and writing-back modules, the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes. To remedy the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.

Dynamic memory management apparatus and method for HLS

The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

FPGA-based dynamic graph processing method

A deep learning heterogeneous computing method based on layer-wide memory allocation, at least comprises steps of: traversing a neural network model so as to acquire a training operational sequence and a number of layers L thereof; calculating a memory room Rrequired by data involved in operation at the ilayer of the neural network model under a double-buffer configuration, where 1&#x2264;i&#x2264;L; altering a layer structure of the ilayer and updating the training operational sequence; distributing all the data across a memory room of the CPU and the memory room of the GPU according to a data placement method; performing iterative computation at each said layer successively based on the training operational sequence so as to complete neural network training.

Deep learning heterogeneous computing method based on layer-wide memory allocation and system thereof

The present invention relates to an optimization method for graph processing based on heterogeneous FPGA data streams. The method can balance processing loads between the CPU processing module and the FPGA processing module during acceleration of graph data processing.

Optimization method for graph processing based on heterogeneous FPGA data streams

A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.

Graph processing optimization method based on multi-FPGA accelerator interconnection

An FPGA-based graph data processing method is provided for executing graph traversals on a graph having characteristics of a small-world network by using a first processor being a CPU and a second processor that is a FPGA and is in communicative connection with the first processor, wherein the first processor sends graph data to be traversed to the second processor, and obtains result data of the graph traversals from the second processor for result output after the second processor has completed the graph traversals of the graph data by executing level traversals, and the second processor comprises a sparsity processing module and a density processing module, the sparsity processing module operates in a beginning stage and/or an ending stage of the graph traversals, and the density processing module with a higher degree of parallelism than the sparsity processing module operates in the intermediate stage of the graph traversals.

FPGA coprocessor with sparsity and density modules for execution of low and high parallelism portions of graph traversals

The present invention relates to a graph-computing-oriented heterogeneous in-memory computing apparatus, comprising a memory control unit, a digital signal processing unit, and a plurality of analog signal processing units using the memory control unit.

Graph-computing-oriented heterogeneous in-memory computing apparatus and operational method thereof

The present invention is related to a storage system of scalable storage for in-memory objects using a DRAM-NVM hybrid memory devices.

Scalable in-memory object storage system using hybrid memory devices

The present disclosure involves a hardware-supported 3D-stacked NVM data compression method and system, involving setting a first identifier to mark a compression state of written-back data, the method at least comprising steps of: dividing the written-back data into a plurality of sub-blocks and acquiring a plurality of first output results through OR operations among the sub-blocks, respectively, or acquiring a plurality of second output results through exclusive OR operations among the sub-blocks, and determining a compression strategy for the written-back data based on the first output results or the second output results; and setting a second identifier to mark a storing means of the written-back data so that the second identifier is in pair with the first identifier, and configuring a storage strategy for the written-back data that includes at least rotating the second identifier.

Hardware-supported 3D-stacked NVM data compression method and system thereof

The present invention relates to a hybrid memory system with live page migration for virtual machine, and the system comprises a physical machine installed with a virtual machine and being configured to: build a channel for a shared memory between the virtual machine and a hypervisor; make the hypervisor generate to-be-migrated cold/hot page information and writing write the to-be-migrated cold/hot page information into the shared memory; make the virtual machine read the to-be-migrated cold/hot page information from the shared memory; and make the virtual machine according to the read to-be-migrated cold/hot page information perform a page migration process across heterogeneous memories of the virtual machine without stopping the virtual machine.

Live page migration for hybrid memory virtual machines

The present invention provides a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management schemes. In the system, NVM is used as large-capacity main memory, and DRAM is used as a cache to the NVM. Some reserved bits in the data structure of TLB and last-level page table are employed effectively to eliminate hardware costs in the conventional hardware-managed hierarchical memory architecture. The cache management in such a heterogeneous memory system is pushed to the software level. Moreover, the invention is able to reduce memory access latency in case of last-level cache misses. Considering that many applications have relatively poor data locality in big data application environments, the conventional demand-based data fetching policy for DRAM cache can aggravates cache pollution. In the present invention, an utility-based data fetching mechanism is adopted in the DRAM/NVM hierarchical memory system, and it determines whether data in the NVM should be cached in the DRAM according to current DRAM memory utilization and application memory access patterns. It improves the efficiency of the DRAM cache and bandwidth usage between the NVM main memory and the DRAM cache.

DRAM/NVM hierarchical heterogeneous memory access method and system with software-hardware cooperative management

In some examples, when a user requests a media device to play media data generated on a virtual machine or receive media data generated by the media device, the media data may be transmitted by sharing physical memory pages among different virtual machines and other virtual components.

Growing community of inventors

Hubei, China

Xiaofei Liao