Altera Corporation

Xiaofei Dong

Hong Shan Neoh

Embodiments of the present invention provide methods and systems for implementing a digital up converter (DUC) in an integrated circuit (IC). The method includes serializing a plurality of inputs to obtain a serial output and then increasing the sample rate of the serial output. Additionally, the method generates signal pairs (sine, cosine) for the desired carrier frequencies using time division multiplexing (TDM). Some of the signal pairs are delayed by one period within the TDM cycle to generate delayed signal pairs. The serial output is distributed, after the increase of the sample rate, to a plurality of filters to further increase the sample rate, each filter outputting a subset of the plurality of inputs using TDM. In one embodiment, the plurality of inputs includes 8 input pairs and the plurality of filters includes 6 Cascaded Integrator-Comb (CIC) filters operating in three-fold TDM. Further, one operation of the method combines the outputs from the plurality of filters with one of the signals from a corresponding signal pair or delayed signal pair. The result of the combination is sent to a digital to analog converter for transmission by one or more antennas.

Implementation of multi-channel intermediate frequency modem for radio communication with a programmable integrated circuit

A programmable logic device can be configured as a fractional rate resampling filter capable of performing downsampling prior to upsampling without modifying the overall filter response. Input data may be received at a first sample rate and may be downsampled to generate downsampled data. Portions of the downsampled data may be respectively output to different filtering paths. Each filtering path may include a cluster of filter components that corresponds to different subfilters of the overall filter response and may be operable to receive and process the different portions of the downsampled data. Outputs of each cluster may be combined to generate output data at a second sample rate. The resampling filter structure can reduce the number of multiplier circuits used by allowing time-division multiplexing among different filter components.

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Sunnyvale, CA, United States of America

Xiaofei Dong