Motorola Corporation

Xiaodong T Zhu

Saied N Tehrani

Eugene Youjun Chen

Herbert Goronkin

Mark A Durlam

Jun Shen

Robert C Kane

Thomas B Harvey, Iii

Ronald N Legge

Michael P Norman

James E Jaskie

Clarence J Tracy

A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.

Multi-layer magnet tunneling junction memory cells

A magnetic random access memory (10) has a plurality of stacked memory cells on semiconductor substrate (11), each cell basically having a portion of magnetic material (12), a word line (13), and sense line (14). Upper sense line (22) is electrically coupled to lower sense line (12) via conductor line (23) with ohmic contacts. In order to read and store states in the memory cell, lower and upper word lines (13, 18) are activated, thereby total magnetic field is applied to portion of magnetic material (11). This stacked memory structure allows magnetic random access memory (10) to integrate more memory cells on semiconductor substrate (11).

Magnetic random access memory having stacked memory cells and

A method of fabricating GMR devices on a CMOS substrate structure with a semiconductor device formed therein. The method includes forming a dielectric system with a planar surface having a roughness in a range of 1 .ANG. to 20 .ANG. RMS on the substrate; disposing and patterning films of giant magneto-resistive material on the planar surface so as to form a memory cell; disposing a dielectric cap on the cell so as to seal the cell and provide a barrier to subsequent operations; forming vias through the dielectric cap and the dielectric system to interconnects of the semiconductor device; forming vias through the dielectric cap to the magnetic memory cell; and depositing a metal system through the vias to the interconnects and to the memory cell.

Method of fabricating GMR devices

Spin polarized apparatus includes a spin polarizing section of magnetic material with an electron input port and a polarized electron port and a transport section of magnetic material with a polarized electron input port electrically coupled to the polarized electron port of the polarizing section and an electron output port. Electrons traversing the polarizing section all have similar spin directions at the output dependent upon the magnetization direction of the polarizing section. Electrons traversing the transport section all have spins in a first direction at the output. The cell has a low resistance when the magnetization direction of the polarizing section is in the first direction (electrons entering the transport section all have spins in the first direction) and a high resistance when the magnetization direction is in an opposite direction (electrons entering the transport section all have spins in the opposite direction).

Spin polarized apparatus

A plurality of layers of magnetic material are stacked in parallel, overlying relationship and separated by layers of non-magnetic material so as to form a multi-layer magnetic memory cell. The width of the cell is less than a width of magnetic domain walls within the magnetic layers so that magnetic vectors in the magnetic layers point along a length of the magnetic layers, and the ratio of the length to the width of the magnetic memory cell is in a range of 1.5 to 10. The magnetic layers are antiferromagnetically coupled when the ratio is less than 4 and ferromagnetically coupled when the ratio is greater than 4.

Multi-layer magnetic memory cells with improved switching characteristics

A multi-layer magnetic memory cell is provided, with magnetic end vectors adjacent the ends of the cell pinned in a fixed direction. To pin the magnetic end vectors, a magnetic field is applied to an end of at least one of the layers of magnetic material in the cell to move the magnetic end vectors in the magnetic material at the end of the cell into a fixed direction. Pinning material is then disposed adjacent to the end to maintain the magnetic end vectors in the magnetic material at the end of the cell in the fixed direction.

MRAM with pinned ends

Multi-layer magnetic tunneling junction memory cells

New types of memory cell structures (20, 40) for a magnetic random access memory are provided. A memory cell (20, 40) has a plurality of cell pieces (21-24) where digital information is stored. Each cell piece is formed by magnetic layers (27, 28) separated by a conductor layer (29). A word line (25, 41) is placed adjacent each cell piece for winding around cell pieces (21-24) and meandering on a same plane on cell pieces (21-24), for example. The invention attains less power consumption and effective usage for a word current.

Multi-piece cell and a MRAM array including the cell

A method for detecting and storing four states contained in a MRAM cell having two layers (11,13) which have different thicknesses is provided. A first magnetic field is applied to the MRAM cell, which causes a magnetoresistive change in the MRAM cell. A first and second states are detected based on the magnetoresistive change. A second magnetic field is further applied to the MRAM cell. A third and fourth states are detected based on the magnetoresistive change due to the second magnetic field.

Method for detecting information stored in a MRAM cell having two

A magnetic random access memory device (10) has a plurality of pairs of memory cells (21a,21b), a column decoder (31), a row decoder (32), and a comparator (60). The pair of memory cells (21a,21b) is designated by column decoder (31) and row decoder (32) in response to a memory address. Complementary bits ('0' and '1') are stored in the pair of memory cells (21a,21b). When the state in the pair of memory cell (21a,21b) is read, both bits in the pair of memory cells (21a,21b) are compared to produce an output at one read cycle time to a bit line (70). This memory device omits a conventional auto-zeroing step so that a high speed MRAM device can be attained.

Method of operating a random access memory device having a plurality of

A method of fabricating an integrated multicolor organic LED array including providing a negative layer and patterning a plurality of different color LED organic layers, one at a time, on the negative layer to form a plurality of different color LEDs in a plurality of areas of a selected array. A first color LED organic layer is patterned on the negative layer in first areas and to define additional areas for additional LEDs laterally separated from the first color LEDs and a final color LED organic layer is deposited in final areas and on previously patterned layers to form a plurality of final color LEDs. Transparent positive contacts are then formed on the final color LED layer in the first and final areas so as to form positive contacts to the first and the final color LEDs.

Method of fabricating an integrated multicolor organic led array

A magnetic memory utilizes a magnetic material to concentrate a magnetic field in a magnetic memory cell element. The magnetic material reduces the amount of current required to read and write the magnetic memory.

Magnetic memory and method therefor

An electron source including selectively impurity doped semiconductor diamond wherein regions of selectively impurity doped regions are inverted with respect to the charge carrier population to provide a conductive path traversed by electrons subsequently emitted into a free-space region from the electron emitter. An inversion mode electron emission device including a selectively impurity doped semiconductor diamond electron emitter, for emitting electrons; a control electrode; and an anode for collecting emitted electrons wherein operation of the device relies on the inducement of an inversion region to facilitate electron transit to an electron emitting surface of the electron emitter.

Method for making inversion mode diamond electron source

An SRAM including first and second RITDs each formed with a heterostructure including a GaSb active layer sandwiched between AlSb barrier layers, which are sandwiched between InAs layers with each RITD having a contact connected to a first of the InAs layers. A TD including an AlSb layer sandwiched between InAS layers. A second InAs layer for each of the RITDs being integrally formed with a first InAs layer of the TD and a read/write terminal connected to a second InAs layer of the TD.

Method of fabricating InAs/GaSb/AlSb material system SRAM

A resonant tunneling FET including a heterostructure FET with a channel layer having a first current contact and a control contact operatively coupled thereto and a resonant tunneling device, including a quantum well layer sandwiched between barrier layers with a resonant tunneling layer affixed to an opposite side of one barrier layer, operably affixed to the heterostructure FET to form a second current contact. The resonant tunneling FET being constructed from a material system which allows the fabrication of additional devices on the same substrate.

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Chandler, AZ, United States of America

Xiaodong T Zhu