Yangtze Memory Technologies Co., Ltd.

Xiaodong Mei

Huangpeng Zhang

Debo Wei

Yu Wang

Xiaojiang Guo

Ke Jiang

Jinze Song

Zhefan Li

According to one aspect of the present disclosure, a memory is provided. The memory may include a row hammer control circuit including a plurality of counters. Each of the plurality of counters may count a number of accesses of one memory row. Each of the plurality of counters may be configured to generate a first count value. The memory may include an adjustment circuit connected with the plurality of counters. The adjustment circuit may reset each of the plurality of counters when each of a plurality of first count values reaches a target threshold. The adjustment circuit may adjust each of the first count values by a same offset value to generate a plurality of second count values. The row hammer control circuit may determine a target memory row according to the plurality of second count values.

Memory and operation method thereof and memory system

Examples of the present application provide operation methods of memories, memory devices and systems. In an example, an operation method includes: in response to a first defective memory cell row of a plurality of memory cell rows in the memory being repaired before packaging, invalidating, in a post-package repair mode, a first repair strategy for repairing the first defective memory cell row before packaging, and configuring a second repair strategy for repairing the first defective memory cell row and storing the second repair strategy.

Operation method of memory, memory and memory system

A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a programming voltage incremented with a first step size; verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size less than the first step size.

Methods for programming a memory device, memory devices, and memory systems

A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least in part, on the second on-die termination configuration value.

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Wuhan, China

Xiaodong Mei