Changxin Memory Technologies, Inc.

Xiaodong Luo

Wei Huang

YiFei Pan

Xing Liu

Bo Yang

An embodiment of the present application provides a test method for tolerance against the hot carrier effect, applied to an I/O circuit of a memory, the I/O circuit having an output terminal, comprising: controlling the output terminal to alternately output a first level and a second level, the first level being higher than the second level; obtaining a degradation rate of an output performance parameter of the I/O circuit according to the first level and the second level; and obtaining tolerance of the I/O circuit against the hot carrier effect based on the degradation rate.

Test method for tolerance against the hot carrier effect

A test method for an alignment error includes: providing a substrate, wherein a first conductive layer and a second conductive layer are arranged on the substrate at intervals, and the first conductive layer and the second conductive layer are arranged in a first direction; acquiring a first distance; acquiring a first resistance of the first conductive layer and a second resistance of the second conductive layer; acquiring an actual distance between the first conductive layer and the second conductive layer according to the first distance, the first resistance, and the second resistance; and acquiring a value of the alignment error between the first conductive layer and the second conductive layer based on the actual distance and a standard distance between the first conductive layer and the second conductive layer.

Test method, adjustment method, test system, and storage medium for alignment error

A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.

Method and device for determining repaired line and repairing line in memory, storage medium, and electronic device

A method for manufacturing a semiconductor device, including: acquiring a substrate, wherein a gate structure is formed on the substrate; implanting first ions into the substrate to form pre-amorphized regions at two sides of the gate structure respectively; implanting second ions into the pre-amorphized regions to form amorphized regions in the pre-amorphized regions respectively; forming first sidewalls each at a respective one of the two sides of the gate structure; performing a second doping process to form first doped regions in the amorphized regions; forming second sidewalls each at a side of a respective first sidewall; and forming a heavily-doped source region and a heavily-doped drain region in the first doped regions respectively.

Method for manufacturing semiconductor device

The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.

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Hefei, China

Xiaodong Luo