Mediatek Singapore Pte. Ltd.

Mediatek Corporation

Silicon Laboratories Inc.

St-ericsson Sa

Xiaochuan Guo

Wen-Chang Lee

Caiyi Wang

Chii-Horng Chen

Donald A Kerth

Russell Croman

Augusto Marques

Augusto Manuel Marques

Lysander Lim

Yen-Horng Chen

Changhua Cao

Shih-Chi Shen

James P Maligeorgos

Jenwei Ko

Brian Green

A class-F power amplifier (PA) with a matching network is disclosed herein. The class-F PA comprises a first switch and a second switch operating in differential mode, with a second harmonic trap circuitry selectively terminating the drain terminals to ground at a second harmonic frequency. The second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. The PA further comprises a common mode trap and a matching network to reduce the imbalance of the drain terminal impedance between first harmonics and third harmonics.

Class-F power amplifier matching network

A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.

Method and apparatus for measuring/compensating mismatches in digitally-controlled oscillator

A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency.

Clock generating apparatus and frequency calibrating method of the clock generating apparatus

Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Time-to-digital converter

A digitally controlled oscillator is provided. The digitally controlled oscillator includes a pair of transistors cross-coupled to each other, a switched capacitor array coupled to the pair of transistors and a plurality of frequency tracking units coupled to the pair of transistors. The pair of transistors provides an output signal. The switched capacitor array tunes a frequency of the output signal. The frequency tracking units tune the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance. A tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances.

Digitally controlled oscillator

A wireless communication device is disclosed wherein isolation buffers couple to respective active circuits or stages of the device to convey test information regarding such active circuits to a test data line from which status information may be collected. The communication device operates in two modes, namely a normal operational mode wherein the isolation buffers effectively short spurious emissions from the active circuits to a ground, and a test mode wherein the isolation buffers may convey test information from a selected active circuit to the test data line. The isolation buffers prevent spurious emissions from escaping the active circuits to which they are coupled and prevent spurious emissions from traveling from active circuit to active circuit over the test data line throughout the wireless device.

System and method for reducing spurious emissions in a wireless communication device including a testing apparatus

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Austin, TX, United States of America

Xiaochuan Guo