National Instruments Corporation

Xiaoce Huang

Rodney W Cummings

Yan Wu

A system and method for controlling access to a dual port shared memory in a system comprising a host computer system and a communication device comprised in or coupled to the host computer system. The communication device includes the shared memory and also includes a local processor which executes a communication application. The shared memory is accessible by both the host computer and the local processor on the communication device. The board or local processor has deterministic and/or real time requirements and is thus the high priority requester, while the host CPU or host computer is the low priority requester. If the high priority side (board) gains the semaphore first, then accesses by the low priority side (host computer) are blocked until the write is finished. In the case of a host read/board write, if the low priority side gains the semaphore first, then the high priority side write can pre-empt the low priority side read. In this case, to avoid data integrity issues, the low priority side is required to verify that it still owns the semaphore after it finishes its read access, and the access fails if the low priority side does not own the semaphore at the time the read is completed. In the case of a host write/board read, if the low priority side gains the semaphore first, then the high priority side does not simply pre-empt to the low priority side as in the high to low data transfer direction. Rather, in this instance, when the high priority side determines that the low priority side owns the semaphore, the high priority side reads previously read data from a local buffer.

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Xiaoce Huang